Intel Corporation

Full-stack Engineer

• Collaborate closely with VLSI designers, user-space software engineers, firmware engineers, and system architects.
• Define and implement innovative features for both current and next-generation products.
• Work with the Linux kernel community and contribute work upstream.

Senior Linux Kernel Developer

Solutions Engineer

• Partner with SoC architecture teams to define and refine system-level chassis and interconnect requirements
• Design and integrate high-performance NoC/interconnect fabrics meeting power, performance, and area (PPA) targets
• Drive integration of IP blocks into SoC platforms, ensuring scalability and performance across products
• Collaborate with fabric IP development teams to enhance or customize reusable components
• Analyze trade-offs across performance, power, and area to influence architectural decisions
• Work closely with physical design teams to address floor planning and implementation constraints
• Support debug, validation, and bring-up activities for integrated SoC platforms
• Collaborate across global, cross-functional teams to deliver complex silicon solutions

SoC Integration Engineer

QA Engineer

• Engage with substrate manufacturing suppliers to influence key technology decisions
• Help define and enable strategies to meet product milestones
• Assess critical risks in technology development activities
• Drive improvements in supplier process technologies
• Synthesize and extract insights from structured and unstructured data using statistics and machine learning

Substrate Quality Engineer

Financial Planning and Analysis

• Provide demand requirements into mid and long-term business plans
• Analyze, recommend and report demand data
• Forecast demand, identify trends including market trends and customer behavior
• Develop strategies to meet demand
• Drive overall Evergreen LRP process and identify risks and opportunities
• Run demand solves for mid-term backend requirements and scenarios
• Integrate and rationalize signals, ensure high level of data quality

Strategic Planning Demand Analyst

QA Automation Engineer

• Resolve designer's tool / methodology issues on the path to TapeOut
• Provide support for design ramp up through training / documentation
• Interact with EDA providers and ensure required tools features are available for the projects with high quality
• Closely partner with PDK/library experts, flow development teams, as well as with product design teams
• Collaborate with EC to provision adequate compute capacity and help debug any associated issues
• Create automation (scripts, checkers, etc.) for installation of design environment (PDKs, EDA tools, licenses, etc.) to simplify and accelerate design processes
• Support the integration of new tools and methods into existing design workflows, ensuring seamless adoption and scalability

Design Automation Engineer – TFM/EDA

Mechanical Engineer

• Lead the functional verification efforts for cutting-edge SoC designs
• Define and implement scalable and reusable verification methodologies
• Develop and execute block, subsystem, and SoC-level verification plans
• Collaborate with SoC architects, RTL designers, and firmware teams
• Oversee the integration of multiple IPs into the SoC environment
• Lead emulation and performance modeling efforts
• Debug and root cause complex issues in pre-silicon environments
• Provide expert guidance and mentorship to technical leads and design verification engineers

Director, SoC Design Engineering

Designer

• Lead cross functional teams across process integration/ device/ yield/ design/OPC/RET/DR and DTP/CAD teams to define and enhance Design for Manufacturability rules for enhanced yield /performance and faster ramp on advanced logic technologies
• Enhance and feed silicon learning / sighting of yield issues for design teams to update layout /DTCO methodologies, flows to capture yield issues early in the design process
• Work and refine yield tools/flows inside foundry and help in inline yield detection and optimization
• Define/Refine DFM methodologies by understanding silicon process flows and predicting and developing rules for avoiding layout and design marginalities by working with cross functional teams

Collateral Design and DFM Engineer

Civil Engineer

• Support development and maintenance of the FASTR database, including field audits and data verification activities
• Participate in field validation efforts, including Point of Connection (POC) lateral X/Y verification, to ensure alignment between design and as-built conditions
• Assist with the testing and validation of new GCE Optimizer software, documenting results and supporting issue resolution
• Support P/ID updates and assist with lateral design development for upcoming construction scopes
• Review and merge vendor drawings with Intel Plan of Record (POR) and lateral reference packages (RPs)
• Assist in creating and maintaining a central repository for 2D and 3D engineering content to support design and construction teams

Construction Engineering Intern

DevOps Engineer

• Assess intrinsic and extrinsic reliability of photonic devices and ICs
• Conduct DOEs to develop reliability models
• Collaborate with cross-functional teams on quality aspects of SiPh technology development
• Determine root causes of failures from reliability testing

Senior Silicon Photonics TD Reliability Engineer

• Collaborates, drives and develops logic design, register transfer level (RTL) coding, and simulation for a CPU required to generate cell libraries, functional units, and the CPU IP block for integration in full chip designs.
• Participates actively in the definition of architecture and microarchitecture features of the CPU being designed.
• Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.
• Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
• Provide technical leadership and support to the design team leadership including proposing creative, innovative methodology and process initiatives to consistently improve efficiency and quality.
• Work closely with architecture and backend teams and with other design teams towards achieving best-in-class products.
• Build a strong and technically vital organization. Cultivate and reinforce appropriate group values, norms and behaviors.

Senior CPU RTL Design Engineer

• Architect, design, and test complex mixed-signal system-on-chip (SoC) and FPGA solutions that interface the microinstruction layer of the quantum computing stack to actual qubits
• Generate complex control signals required to drive and read qubit states with precision and reliability
• Perform signal integrity analysis and optimization for qubit chips to ensure optimal performance
• Apply electromagnetic (EM) modeling and simulation tools for signal integrity and crosstalk analysis
• Work in close collaboration with both software/algorithms and qubit development teams to create integrated solutions
• Bridge the gap between quantum physics and practical electronic implementation

Qubit Control IC Designer

Architect

• Drives end-to-end development for substrate design from concept through tape out
• Implements physical layout and routing of the package design
• Performs substrate fit and routing studies to establish design, performance, and cost tradeoffs
• Works closely with silicon and hardware teams to optimize silicon-package-board performance and pinout
• Defines substrate design rules, conducts internal and external reviews, analyzes data, and resolves DRCs to optimize package design
• Completes documentation and collateral into the product lifecycle management system of record

Packaging Design Architect

• Define and own the thermal architecture for complex electronic systems
• Develop thermal budgets, airflow strategies, and cooling solutions
• Lead CFD and FEA thermal simulations using tools such as Ansys Icepak, FloTHERM, 6SigmaET, or COMSOL
• Drive trade-off analyses between thermal performance, acoustics, cost, weight, and form factor
• Partner with silicon and power teams to influence chip floorplans, package selection, and power delivery for thermal optimization
• Specify and qualify thermal interface materials (TIMs), heatsinks, fans, pumps, cold plates, and related components
• Lead thermal characterization, bring-up, and validation in the lab; correlate models to measured data
• Mentor junior thermal engineers and establish best practices, design guidelines, and review processes
• Engage with suppliers and ODM/OEM partners on thermal design reviews and DFx activities
• Represent thermal engineering in cross-functional architecture reviews and executive readouts.

Senior Thermal Architect

• Assist in designing, simulating, and verifying digital and/or analog circuits to meet Intel's high-performance standards
• Contribute to schematic entry, timing analysis, and optimization for power, performance, and area
• Perform noise glitch and signal integrity analysis to ensure robust circuit designs
• Collaborate with cross-functional teams to identify and implement innovative solutions for low-power and high-performance designs
• Perform debugging, hardware simulations, and circuit testing to validate design functionality
• Utilize and navigate EDA tools to execute floor planning and clock gating tasks
• Apply semiconductor device physics knowledge to analyze and improve circuit tradeoffs
• Continuously learn, adapt, and contribute to process improvements in alignment with Intel's culture of innovation

Analog Circuit Design Engineer – Graduate Intern

Marketing

• Contribute to the development and execution of marketing strategies across brand, product, content, and campaign domains.
• Assist with market research, content creation, and performance tracking to support Intel's brand positioning and customer engagement.
• Collaborate with cross-functional teams to deliver impactful marketing initiatives across digital and traditional channels.
• Learn and apply knowledge, build skills, and explore future career opportunities through hands-on experience and projects that support Intel's business goals in a collaborative environment.
• Support the Channel Marketing Manager in overseeing the end-to-end MDF lifecycle.
• Ensure all partner marketing activities align with the Outcome-Based Guidebook and corporate brand guidelines throughout the campaign execution process until funds are released.
• Monitor campaign execution and unspent funds, and proactively recommend reallocation of expiring budgets.
• Act as the internal point of contact for partners, coordinating with our third-party agency.
• Develop and maintain dashboards that track the performance of MDF-funded partner activities.