Intel Corporation

Controller

• Lead a global H2R controllership team and set clear goals, priorities and performance standards
• Own technical accounting from grant to settlement including valuation oversight, expense attribution, forfeiture and performance assessments and related tax effects for Stock Based Compensation ASC 718
• Govern accrual methodologies for global bonus and sabbatical programs under ASC 710
• Partner with HR and Legal on execution and related reporting for Restructuring and Severance ASC 420 and ASC 712
• Oversee Health and Welfare plan financial reporting and regulatory filings including 11K
• Manage proxy reporting inputs with Legal including executive compensation tables and equity program metrics
• Maintain and enhance accounting policies and internal controls
• Drive global standardization and consistent application of accounting guidance
• Lead forecasting and scenario analysis across SBC, bonus, benefits, sabbatical and restructuring for H2R Role in CAO Transformation

Hire to Retire Controller

Full-stack Engineer

• Design, implement, verify, and support the enablement and adoption of advanced hardware design tools, flows, and methodologies
• Define comprehensive methodologies for hardware development related to technology nodes and EDA tool enabling
• Create and verify unique hardware designs, assemble design platforms, and integrate components into hierarchical systems
• Provide deployment coverage for end-to-end EDA tool testing on new technology nodes
• Develop, test, and analyze engineering design automation tools, flows, and methodologies to improve efficiency and optimize power and performance
• Support development and enhancement of platforms, databases, scripts, and tool flows for design automation
• Build deep understanding of digital design, verification, structural and physical layout, fullchip integration, power and performance, clocking, and/or timing to enhance future TFM development
• Collaborate with EDA vendors on defining and early testing of next-generation design tools

EDA Tools Software Engineer

Financial Planning and Analysis

• Drive Foundry's near- and long-term capital forecast to support capacity planning and profitability.
• Lead capital POR/LRP forecast, BOD/Audit finance committee updates, and quarterly CPA approvals.
• Partner with FSP (Foundry Strategic Planning) in capital related activities.
• Engage executive management and convey clear messages.
• Perform robust financial analysis, modeling, and data manipulation with tools like Power BI / Power Query.

Finance Lead

Manager

• Oversee the full lifecycle of federal government contracts and subcontracts.
• Ensure the organization remains in 100% compliance with federal regulations while mitigating legal risk.
• Act as the primary liaison between the company and Government Contracting Officers (COs).
• Manage the "Cradle-to-Grave" contract process, including RFP analysis, proposal development, negotiation, administration, and closeout.
• Act as the subject matter expert on Federal Acquisition Regulations (FAR) and Defense Federal Acquisition Regulation Supplement (DFARS).
• Lead negotiations on complex terms, conditions, and pricing with government agencies and prime contractors.
• Identify potential contractual risks and develop mitigation strategies.
• Oversee the issuance and management of subcontracts, ensuring mandatory flow-down clauses are included.
• Serve as the lead point of contact for DCAA/DCMA audits and ensure all documentation is always “audit-ready”.
• Manage a diverse portfolio including FFP, CPFF, CPIF, and Other Transaction Authority (OTA) agreements.
• Advise leadership on the pros/cons of different contract vehicles.

Federal Contract Manager

Mechanical Engineer

• Set and refine a multi-generational roadmap for HSIO and D2D IP development
• Engage directly with senior Intel architects and executives to define IP landing zones
• Drive IP development across architecture, logic, validation and analog design teams
• Manage competing requirements, schedules, and resource balancing across multiple functional teams
• Ensure high quality and on-time IP delivery, including proactive risk management
• Lead and develop a high-performing global team of engineers
• Foster a culture where issues surface and are addressed early
• Drive efficiency throughout the development cycle, including the adoption of AI solutions

Senior Director, IO Analog Design Engineering

• Contribute to diverse areas of Silicon Hardware Engineering
• Help in designing, building, and testing technology for Intel's processors and platforms
• Participate in roles related to Silicon Architecture, Circuit Design, Verification, and Validation

Software Engineering Intern, Graduate

Hardware Engineer

• Help us to transform raw materials into the silicon that powers our advanced computing infrastructure.
• You'll be involved in designing, building, and testing the technology that's at the core of Intel's powerful processors and platforms.
• Contribute to diverse areas of Silicon Hardware Engineering, including roles in Silicon Architecture, Circuit Design, General Design, Layout, Logic, Photonics, Physical Design, TFM, Verification, Product Engineering, and Validation and Debug.

Hardware Engineering Intern, Graduate

Engineer

• Drive the enablement, validation, and complex debugging of memory subsystems
• Provide strategic oversight of memory IO interfaces
• Define and execute the overarching validation and debug strategy for memory IO interfaces
• Lead the reproduction and root-cause analysis of high-priority customer-submitted failure sightings
• Ensure all customer memory IO interfaces meet industry-standard electrical signal integrity (SI) compliance
• Define Memory Reference Code (MRC) requirements for validation and margin optimization
• Act as the primary liaison between Intel Silicon Engineering, BIOS/Firmware teams, and the customer
• Manage and drive task force environments to resolve critical bugs
• Communicate effectively with cross-functional teams and external customers

Memory Debug Engineer

• Designing, building, and testing the technology at the core of Intel's processors
• Contributing to diverse areas of Silicon Hardware Engineering
• Involvement in roles like Circuit Design, Verification, and Product Engineering

Hardware Engineering Intern, Bachelor’s

• Design, build, and test technology for Intel's processors
• Contribute to Silicon Hardware Engineering areas
• Collaborate on Silicon Architecture, Circuit Design, and Validation

Software Engineering Intern, Bachelor’s

Designer

• Design, develop, and implement analog circuits in advanced semiconductor process nodes for analog and mixed‑signal IP blocks
• Create floorplans, perform transistor‑level circuit design, extract chip parameters, and run detailed analog simulations and behavior modeling
• Develop comprehensive test plans aligned with circuit and block micro‑architecture specifications; analyze and evaluate silicon and pre‑silicon test outcomes
• Verify and optimize circuit functionality for power, performance, area, timing, and yield (PPA) targets
• Investigate, track, and resolve circuit‑level and performance issues while providing clear status updates to cross‑functional teams
• Collaborate with architecture and layout teams to ensure robust, high‑quality electrical behavior and best‑in‑class circuit operation
• Reduce leakage, improve power efficiency, and enhance signal integrity across multiple circuit types

Experienced Analog Designer

Cloud Engineer

• Assess infrastructure across Windows, Linux, AIX, and Solaris environments to determine migration readiness and dependencies.
• Design and recommend cloud migration strategies (e.g., rehost, replatform, refactor) tailored to business needs and technical constraints.
• Plan and execute migrations to cloud platforms such as Amazon Web Services (AWS), Microsoft Azure, and Google Cloud (GCP).
• Automate deployment and configuration using scripting and Infrastructure as Code tools (Terraform, Bicep, ARM, CloudFormation).
• Troubleshoot and optimize performance, security, and cost-efficiency post-migration.
• Collaborate with engineering, operations, and security teams to ensure seamless integration and compliance with standards.
• Document migration plans, runbooks, and best practices to support continuity and knowledge transfer.

Cloud Migration Engineer

• Develop IP verification plans, test benches, and verification environments
• Execute verification plans and define system simulation models
• Replicate, root cause, and debug issues in the pre-silicon environment
• Collaborate with architects, RTL developers, physical design teams, and other DV teams
• Document test plans and drive technical reviews of plans and proofs
• Maintain and improve existing functional verification infrastructure

Verification Engineer

• Performs functional verification of graphics logic components, including 3D graphics, media, and display, to ensure design will meet specification requirements
• Defines and develops scalable and reusable IP verification plans, test benches, and architecture for verification environment to ensure coverage to confirm to graphics microarchitecture specifications
• Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs
• Replicates, root causes, and debugs issues in the presilicon environment
• Finds and implements corrective measures to resolve failing tests
• Collaborates with GPU architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features and to meet functional, performance, and power goals
• Documents test plans and drives technical reviews of plans and proofs with design and architecture teams
• Maintains and improves existing functional verification infrastructure and methodology
• Participates in the definition of verification infrastructure and related TFMs needed for functional design verification

GPU Design Verification Engineer

• Design, develop and deliver circuit building block schematic, perform pre layout and post layout design optimization to meet design specification across PVT, process variation sensitivity analysis, aging, EOS, RV checks for design reliability
• Work with custom layout team to define plan (floorplan, routing, matching, metal grid etc) to meet circuit performance
• Collateral generation like circuit integration spec, and be a key driver to drive transition to AI tool-based design BMOD, timing model, power model, ICCT, IBIS, alpha numbers
• Own specifications and design verification plans covering functionality, performance and reliability meeting high volume productization requirement
• Collaborate with logic designer, logic verification designer, structural physical design engineers, integration engineers, signal integrity and power deliver engineer to define clear collateral handoff requirements to ensure efficient IP integration
• Perform post silicon data analysis and debug and make necessary design enhancement to meet design specification
• Conduct design reviews; actively contribute to design reviews
• Represent the team on related IP in cross-functional meetings and co-ordination of deliverables
• Work with external IP vendors as point of contact for analog designs