Senior Reliability Engineer – PDK, TFM

Intel Corporation

Reliability PDK and TFM engineer developing design rules, EDA flows, and reliability collateral. Enabling Intel Foundry customer designs across leading technology nodes.

Posted 9/8/2026full-timeHillsboro • Arizona, California, Oregon • 🇺🇸 United StatesSenior💰 $149,600 - $284,580 per yearWebsite

Core Competencies

Role fit

Core Competencies

Use this summary to align your resume positioning with the role.

Demonstrates expertise in PDK development, reliability design rules, and EDA tool and flow development, with a strong focus on quality assurance and design reliability validation. Capable of driving quality enhancement projects and collaborating effectively in diverse environments.

Highest-signal resume keywords

PDK DevelopmentReliability Tool And FlowDesign For ReliabilityQuality AssuranceEDA Tool Development

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Reliability Design RulesCircuit DesignIP DesignSoC Design ValidationTechfile GenerationProgramming SkillsDesign Impact AssessmentReliability VerificationPhysics Of ReliabilityQuality Enhancement Projects

Soft Skills

Excellent Communication SkillsTeam PlayerFlexibilityAttention To DetailAdaptability

Tools & Technologies

EDA ToolsDesign Flow ApplicationsReliability Verification ToolsQuality Assurance Tools

Industry Keywords

Reliability MechanismsBenchmarking AnalysisTFMIP EcosystemsAgingBTIHCIElectro-MigrationHigh-Voltage DesignEOS

About the role

Key responsibilities & impact

Define and generate reliability-related PDK design rules and collateral covering reliability mechanisms
Conduct quality assurance and benchmarking analysis
Drive EDA tool and flow enablement in synergy with PDK development
Work with internal partners and EDA vendors to deliver competitive TFM for design reliability verification
Conduct competitive analysis and benchmark technology reliability
Plan and deliver PDK, design rules, design collateral, TFM, and IP ecosystems
Enable internal and external customer design on Intel technology
Drive quality enhancement projects and efficiency and innovation initiatives

Requirements

What you’ll need

Bachelor's degree in electrical engineering, physics or a related field and 6+ years of relevant work experience, or 4+ years of relevant experience and a master's degree, or a PhD degree with 2+ years of relevant experience
3+ years' experience in PDK development, reliability tool and flow, design for reliability, circuit, IP and SoC design reliability validation using PDK, or EDA tool and flow development
Excellent written and verbal communication and presentation skills
Passion for quality and attention to details and procedures
Demonstrated capability to drive quality enhancements projects
Strong team player with ability to work in diverse multi-cultural environments
Flexibility and adaptability to ensure program commitments are met on time
Hands-on experience on PDK development and validation
Knowledge and understanding of PDK fundamentals, reliability design rules, and their implementation in PDK and TFM
Capability to use AI or programming skills to write code, agents, or scripts for design rule, techfile generation, and quality assurance
Experience with PDK, EDA tool/flow development, design flow application, and IP and SoC design validation and sign-off
Experience in design impact and risk assessment in reliability areas
Experience and knowledge of reliability verification and physics, including aging, BTI, HCI, electro-migration, high-voltage design, EOS, and ESD
Experience and skills in program management and stakeholder management

Benefits

Comp & perks

Health, dental, and retirement benefits
14 paid holidays per calendar year
Three weeks of paid vacation
Four-week paid sabbatical every four years of employment
Five bonuses per year dependent on overall company and personal performance
Employee stock purchase program
Competitive pay
Stock bonuses
Hybrid work model allowing employees to split time between working on-site and off-site