Junior Verification Engineer

Intel Corporation

Junior Verification Engineer verifying high-speed SerDes IP for PCIe and Ethernet interfaces. Developing mixed-signal verification environments, DSP validation, and firmware-hardware co-verification.

Posted 9/4/2026full-timeJerusalem • 🇮🇱 IsraelJuniorWebsite

Core Competencies

Role fit

Core Competencies

Use this summary to align your resume positioning with the role.

Demonstrates expertise in verification of high-speed SerDes mixed-signal IP, with a strong foundation in digital design and computer architecture. Proficient in developing advanced verification environments and conducting firmware/hardware joint verification.

Highest-signal resume keywords

Verification Lifecycle ManagementDigital DesignSystemVerilog/UVMPython ProgrammingHigh-Speed Protocols

ATS Keywords

Tailor your resume

Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard Skills

VerificationMixed-Signal IPDigital DesignComputer ArchitectureFirmware VerificationDatapath ValidationRoot-Cause AnalysisAI-Assisted ToolsRTL DesignCoverage-Driven Verification

Soft Skills

Analytical MindsetProblem-SolvingAdaptabilityCollaboration

Industry Keywords

SerDesPCIeEthernetAnalog SimulationVerification Environments

Tech Stack

Tools & technologies

Python

About the role

Key responsibilities & impact

Perform constrained-random and coverage-driven verification of complex high-speed SerDes mixed-signal IP
Develop advanced verification environments
Validate DSP datapaths
Conduct firmware/hardware joint verification
Use AI-assisted tools as part of the daily engineering workflow
Contribute across the verification lifecycle from specification through tape-out sign-off

Requirements

What you’ll need

Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science
0–3 years of industry or academic experience in hardware design or verification
Solid grasp of digital design, computer architecture, and software programming
Analytical mindset and ability to root-cause problems
Ability to thrive in a dynamic, multi-disciplinary environment
Hands-on exposure to SystemVerilog/UVM or Python is advantageous but not required
Familiarity with mixed-signal or analog simulation concepts is a nice-to-have
Knowledge of high-speed protocols such as PCIe or Ethernet is a nice-to-have
Prior internship or experience in RTL design or verification is a nice-to-have
Strong academic record; top graduating students are encouraged to apply

Benefits

Comp & perks

Collaborative and innovative work environment
Exposure to the full verification lifecycle, from specification to tape-out sign-off
Modern tooling, including AI-assisted engineering
Real growth path from day one