SiTime

Account Manager

• Take ownership of an assigned geographic territory / account set
• Drive growth and expansion within the territory by increasing account penetration
• Identify new customers, opportunities, and applications
• Ensure consistent pipeline build-up to support long-term growth
• Manage a portfolio of long-tail accounts maintaining consistent pipeline activity to support revenue goals
• Connect with customers to understand basic requirements and introduce SiTime solutions
• Run focused, efficient conversations with clear next steps
• Ensure steady movement of deals toward design-in and potential wins
• Work closely with distribution partners to drive demand generation and support customer engagement

Account Manager – Customer Expansion

Engineer

• Develop, optimize, and characterize packaging processes for WLCSP technologies
• Perform root cause analysis and implement corrective and preventive actions
• Collaborate with R&D, design, equipment, and manufacturing teams for seamless process transfer
• Lead or participate in cross-functional teams for new product introduction (NPI) and process improvement projects
• Conduct process capability analysis and drive continuous improvement initiatives

Senior Packaging Engineer

Mechanical Engineer

• Design of Analog and Mixed-Signal circuits, meeting their architectural requirements and technical specifications
• Contribute to the architectural definition of the design, and also to chip integration
• Perform the necessary calculations, design and verification simulations to ensure building blocks meet specifications, at the schematic level and after post layout extraction, while fully provisioning for DFT and DFM
• Work closely with Layout Designers to ensure the layout is completed properly, using all best known methods
• Document assigned blocks, and hold preliminary and final design reviews
• Actively participate in the chip bring up, evaluation and characterization, with emphasis on owned blocks
• Address questions and issues related to his/her blocks raised by cross-functional personnel, such as Product, Characterization, Test, or Application Engineers.
• Drive other projects as needed by management or as business needs change.

Engineer II, Analog Mixed-Signal Design

• Design analog and mixed-signal circuits meeting architectural requirements and technical specifications
• Contribute to the architectural definition of the design and chip integration
• Perform calculations, design and verification simulations to ensure building blocks meet specifications at the schematic level and after post-layout extraction, while fully provisioning for DFT and DFM
• Work closely with Layout Engineers to validate proper layout, using all best-known methods
• Document assigned blocks, and hold preliminary and final design review meetings
• Actively participate in the chip bring up, evaluation and characterization, with emphasis on owned blocks
• Work cross-functionally with Product, Characterization, Test, and Application Engineers on issues related to owned circuit blocks
• Support other projects as needed by management or as business needs change

Senior Engineer, Analog Mixed-Signal Design

• Lead top-level chip-planning and perform functional-block-level, block-level, sub-block level, leaf cell, standard cell custom layouts for CMOS and BiCMOS circuits
• Perform schematic-driven layout and design constraints
• Design die-area efficient layouts according to circuit designer requirements
• Perform block or top-level layout designs
• Perform floor-planning, power line planning, shielding, and device-matching layout
• Verify layouts. Pass DRC, LVS, and ERC
• Contribute to various chip-level routing and layout needs
• Perform chip level integration, verifications, and tape-out
• Support other projects as needed by management
• Train junior layout engineers and offshore layout contractors
• Contribute to developing common best practices and workflow across all sites
• Contribute to build process and procedures to achieve high layout quality

Senior Engineer, Layout Design

Full-stack Engineer

• responsible for lead and supervise circuit design and chip development projects
• define device and circuit architectures for next-generation products
• design circuit blocks for future products
• review circuits and architectures to ensure high quality designs
• propose improvements and implement methodologies for IC development
• develop precision timing circuit architectures, design innovative circuits with aggressive technical performance specifications, performing transistor-level design and simulations
• plan and execute circuit designs that address demanding frequency stability, phase noise and power consumption, silicon die area specifications
• perform technology, architecture, circuit design, and parametric design trade-offs to accomplish spec-compliant designs
• ensure first-pass success on Analog CMOS circuit solutions, fully leveraging SiTime’s innovative MEMS technology offerings
• collaborate with Digital Design Engineers, CAD, Systems Engineering, ATE Engineering and Applications teams to design chips with DFT, DFM, achieve rapid silicon bring-up and fast time-to-production release
• deploy robust design methodology and ensure comprehensive design reviews
• supervise and guide Senior Analog Circuit Designers
• supervise Analog Circuit Physical Design Layout and edit layouts
• perform post-layout parasitic-extraction and back-annotated simulations to validate design across Process, Voltage, Temperature
• perform requisite Monte Carlo Analysis on key circuits to ensure Six-Sigma quality and yields
• participate in bring-up of silicon prototypes
• initiate Design-of Experiments for Root Cause Analysis, investigate anomalous observations in silicon across PVT conditions, and propose solutions
• drive other projects as needed by management or as business needs change

Principal Engineer, Analog Mixed-Signal Design

Designer

• The Sr. Layout Design Engineer will lead top-level chip-planning and perform block-level custom layouts for CMOS and BiCMOS circuits.
• Review, and coordinate work content performed by offshore layout designers.
• Train junior layout engineers and offshore layout contractors.
• Contribute to developing standard layout methodologies across sites.
• Contribute to build process and procedures to achieve high layout quality.
• Requires remote interfacing with local and global design and layout teams in multiple design centers across different time zones.
• Lead Top-level chip-planning and perform functional-block-level, block-level, sub-block level, leaf cell, standard cell custom layouts for CMOS and BiCMOS circuits.
• Perform schematic-driven layout and design constraints.
• Design die-area efficient layouts according to circuit designer requirements.
• Perform block or top-level layout designs.
• Perform floor-planning, power line planning, shielding, and device-matching layout.
• Verify layouts. Pass DRC, LVS, and ERC.
• Contribute to various chip-level routing and layout needs.
• Perform chip level integration, verifications, and tape-out.
• Support other projects as needed by management.
• Contribute to developing common best practices and workflow across all sites.
• Contribute to build process and procedures to achieve high layout quality.

• lead top-level chip-planning and perform block-level custom layouts for CMOS and BiCMOS circuits
• review, and coordinate work content performed by offshore layout designers
• train junior layout engineers and offshore layout contractors
• contribute to developing standard layout methodologies across sites
• contribute to build process and procedures to achieve high layout quality
• requires remote interfacing with local and global design and layout teams in multiple design centers across different time zones
• perform schematic-driven layout and design constraints
• design die-area efficient layouts according to circuit designer requirements
• perform block or top-level layout designs
• perform floor-planning, power line planning, shielding, and device-matching layout
• verify layouts and pass DRC, LVS, and ERC
• contribute to various chip-level routing and layout needs
• perform chip level integration, verifications, and tape-out
• support other projects as needed by management

Senior Layout Engineer

• Lead top-level chip-planning and perform functional-block-level, block-level, sub-block level, leaf cell, standard cell custom layouts for CMOS and BiCMOS circuits
• Perform schematic-driven layout and design constraints
• Design die-area efficient layouts according to circuit designer requirements
• Perform block or top-level layout designs
• Perform floor-planning, power line planning, shielding, and device-matching layout
• Verify layouts. Pass DRC, LVS, and ERC
• Contribute to various chip-level routing and layout needs
• Perform chip level integration, verifications, and tape-out
• Train junior layout engineers and offshore layout contractors
• Contribute to develop common best practices and workflow across all sites
• Contribute to build process and procedures to achieve high layout quality

Administration

• Ensure that SiTime Finland is a comfortable and productive place to work
• Welcome visitors and incoming calls in a professional manner
• Manage office shipments and deliveries
• Set up conference calls, meetings (on-site and off-site), presentations, etc.
• Provide new hires with the badge, parking permit etc.
• Assist travel management
• Assist financial accounting with local partners
• Align company HR guidelines with local practices
• Coordinate with landlord on safety
• Manage correspondence and documentation as needed

Account Manager – Customer Expansion

Senior Packaging Engineer

Engineer II, Analog Mixed-Signal Design

Senior Engineer, Analog Mixed-Signal Design

Senior Engineer, Layout Design

Principal Engineer, Analog Mixed-Signal Design

Senior Engineer, Layout Design

Senior Layout Engineer

Senior Layout Engineer

Office Administrator