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SiTime

Principal Engineer, Analog Mixed-Signal Design

SiTime

Principal Engineer leading Analog Mixed-Signal Design projects at SiTime. Responsible for overseeing circuit design and supervising the development of next-generation products.

Posted 7/15/2026full-timeRemote • 🇩🇪 GermanyLeadWebsite

Core Competencies

Role fit
Core Competencies

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Demonstrates expertise in Analog Circuit Design, including Circuit Architecture Development, Design Verification, and Chip Validation. Proficient in leading teams and implementing methodologies for high-performance, low-noise circuit solutions.

Highest-signal resume keywords
Analog Circuit DesignCircuit Architecture DevelopmentLow-Jitter Frac-N PLL ImplementationChip Validation and CharacterizationSupervision of Design Engineers

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills
Circuit DesignTransistor-Level DesignSimulation of Analog Building BlocksDesign PartitioningPost-Layout Parasitic ExtractionMonte Carlo AnalysisDFT and DFM TechniquesHigh-Speed Operational AmplifiersADC and DAC DesignTemperature Sensor Design
Soft Skills
LeadershipCollaborationProblem-SolvingCommunication
Tools & Technologies
MEMS TechnologyDesign Automation ToolsSimulation Software
Certifications & Qualifications
MS Degree in Electrical EngineeringPhD Preferred
Industry Keywords
Analog CMOS Circuit SolutionsPhase NoisePower ConsumptionSilicon PrototypesSix-Sigma Quality

About the role

Key responsibilities & impact
  • responsible for lead and supervise circuit design and chip development projects
  • define device and circuit architectures for next-generation products
  • design circuit blocks for future products
  • review circuits and architectures to ensure high quality designs
  • propose improvements and implement methodologies for IC development
  • develop precision timing circuit architectures, design innovative circuits with aggressive technical performance specifications, performing transistor-level design and simulations
  • plan and execute circuit designs that address demanding frequency stability, phase noise and power consumption, silicon die area specifications
  • perform technology, architecture, circuit design, and parametric design trade-offs to accomplish spec-compliant designs
  • ensure first-pass success on Analog CMOS circuit solutions, fully leveraging SiTime’s innovative MEMS technology offerings
  • collaborate with Digital Design Engineers, CAD, Systems Engineering, ATE Engineering and Applications teams to design chips with DFT, DFM, achieve rapid silicon bring-up and fast time-to-production release
  • deploy robust design methodology and ensure comprehensive design reviews
  • supervise and guide Senior Analog Circuit Designers
  • supervise Analog Circuit Physical Design Layout and edit layouts
  • perform post-layout parasitic-extraction and back-annotated simulations to validate design across Process, Voltage, Temperature
  • perform requisite Monte Carlo Analysis on key circuits to ensure Six-Sigma quality and yields
  • participate in bring-up of silicon prototypes
  • initiate Design-of Experiments for Root Cause Analysis, investigate anomalous observations in silicon across PVT conditions, and propose solutions
  • drive other projects as needed by management or as business needs change

Requirements

What you’ll need
  • MS Degree in Electrical Engineering, PhD preferred
  • Minimum 10 years of high-performance analog circuit design experience
  • Proven track record at each stage of the following: Circuit Architecture development and technical feasibility studies, Design partitioning for phase noise / power budgeting, Writing detailed block-level specifications, Detailed design, test bench development, and simulation of basic analog building blocks and one or more of the following: ADCs, DACs, Temperature Sensors, PLL, high-speed Operational Amplifiers, On-chip Regulators, Band gap Circuits
  • Expert-level experiential knowledge of architecting and implementing ultra low-jitter, power-efficient Frac-N PLLs
  • Experiential knowledge of ultra-low phase-noise design, power supply noise considerations, device matching, parasitic extraction, signal integrity, ESD
  • Supervision of Junior and Senior Analog Design Engineers
  • Supervision of layout and editing of critical blocks
  • Chip-level design and verification of complex mixed-signal chips
  • Chip validation, Characterization, Qualification, adherence to production release to production 3 years of prior lead/supervisory/managerial experience preferred

Benefits

Comp & perks
  • quarterly bonus tied to the achievement of innovation goals
  • equity grants
  • comprehensive and highly competitive compensation package
  • remote work options