Senior Engineer, Layout Design

SiTime

Sr. Layout Design Engineer leading chip-planning and block layouts for CMOS and BiCMOS circuits at SiTime.

Posted 7/15/2026full-timeRemote • 🇩🇪 GermanySeniorWebsite

Core Competencies

Role fit

Core Competencies

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Expertise in layout design for CMOS and BiCMOS circuits, with a strong focus on DRC, LVS, and ERC verification. Proven ability to lead chip-level integration and training of junior engineers while ensuring high layout quality and efficiency.

Highest-signal resume keywords

Layout Design for Analog and Full-Custom Digital BlocksCadence Virtuoso Design EnvironmentDRC/LVS/ERC Debugging with Cadence PVS or Mentor CalibreChip-Level Floor Planning and IntegrationDevice Matching and Signal Integrity Solutions

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Custom Layouts for CMOS and BiCMOS CircuitsSchematic-Driven LayoutFloor-Planning and Power Line PlanningDevice-Matching LayoutChip-Level Integration and Tape-OutDebugging DRC/LVS/ERCProductivity-Enhancing Tools and Design ScriptsParasitic and Crosstalk UnderstandingElectro-Migration and IR Drop SolutionsAttention to Detail in Layout Techniques

Soft Skills

OrganizedAccurateAttention to Detail

Tools & Technologies

Cadence VirtuosoCadence PVSMentor Calibre

Industry Keywords

Chip-Level RoutingLayout QualityBest Practices DevelopmentLayout Design ConstraintsAnalog Block Integration

About the role

Key responsibilities & impact

Lead top-level chip-planning and perform functional-block-level, block-level, sub-block level, leaf cell, standard cell custom layouts for CMOS and BiCMOS circuits
Perform schematic-driven layout and design constraints
Design die-area efficient layouts according to circuit designer requirements
Perform block or top-level layout designs
Perform floor-planning, power line planning, shielding, and device-matching layout
Verify layouts. Pass DRC, LVS, and ERC
Contribute to various chip-level routing and layout needs
Perform chip level integration, verifications, and tape-out
Support other projects as needed by management
Train junior layout engineers and offshore layout contractors
Contribute to developing common best practices and workflow across all sites
Contribute to build process and procedures to achieve high layout quality

Requirements

What you’ll need

BA/BS Degree in Layout Design or related field or equivalent experience
10 years’ experience with layout design for analog and full-custom digital blocks
Proficient in using layout editing tools in the Cadence Virtuoso design environment
Solid working knowledge of debugging DRC/LVS/ERC with Cadence PVS or Mentor Calibre
Conceptual understanding of layout topics such as parasitic, matching, crosstalk, transistor layout dependent effects, latch-up, IR drop, electro migration (EM), and deep N-well and NTN isolation
Strong capability of solving device matching, electro-migration, signal integrity and power distribution problems while meeting area constraints
Experience in chip-level floor planning and analog block integration
Experience chip level integration, verifications, and tape-out
Ability to use productivity-enhancing tools and design scripts to further automate tasks is also desirable
Attention to detail, organized, accurate and can produce efficient layout techniques

Benefits

Comp & perks

quarterly bonus tied to the achievement of innovation goals
equity grants