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About the role
Key responsibilities & impact- Lead top-level chip-planning and perform functional-block-level, block-level, sub-block level, leaf cell, standard cell custom layouts for CMOS and BiCMOS circuits
- Perform schematic-driven layout and design constraints
- Design die-area efficient layouts according to circuit designer requirements
- Perform block or top-level layout designs
- Perform floor-planning, power line planning, shielding, and device-matching layout
- Verify layouts. Pass DRC, LVS, and ERC
- Contribute to various chip-level routing and layout needs
- Perform chip level integration, verifications, and tape-out
- Train junior layout engineers and offshore layout contractors
- Contribute to develop common best practices and workflow across all sites
- Contribute to build process and procedures to achieve high layout quality
Requirements
What you’ll need- AA/AS Degree in Layout Design or related field or equivalent experience
- 10 years’ experience with layout design for analog and full-custom digital blocks
- Experience TSMC 180nm, 65nm, 22nm process technologies
- Proficient in using layout editing tools in the Cadence Virtuoso design environment
- Solid working knowledge of debugging DRC/LVS/ERC with Cadence PVS or Mentor Calibre
- Conceptual understanding of layout topics such as parasitic, matching, crosstalk, transistor layout dependent effects, latch-up, IR drop, electro migration (EM), and deep N-well and NTN isolation
- Strong capability of solving device matching, electro-migration, signal integrity and power distribution problems while meeting area constraints
- Experience in chip-level floor planning and analog block integration
- Experience chip level integration, verifications, and tape-out
- Ability to use productivity-enhancing tools and design scripts to further automate tasks is also desirable
- Must be able to lift, push, and pull up to 5 lbs.
Benefits
Comp & perks- comprehensive and highly competitive compensation package designed to attract top talent
- quarterly bonus tied to the achievement of innovation goals
- equity grants, providing a meaningful opportunity to share in the company’s future growth and success
ATS Keywords
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Hard Skills & Tools
layout designCMOS circuitsBiCMOS circuitsschematic-driven layoutDRCLVSERCchip-level integrationanalog block integrationfloor planning
Soft Skills
trainingproblem solvingcollaborationworkflow developmentbest practices
Certifications
AA/AS Degree in Layout Design