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About the role
Key responsibilities & impact- lead top-level chip-planning and perform block-level custom layouts for CMOS and BiCMOS circuits
- review, and coordinate work content performed by offshore layout designers
- train junior layout engineers and offshore layout contractors
- contribute to developing standard layout methodologies across sites
- contribute to build process and procedures to achieve high layout quality
- requires remote interfacing with local and global design and layout teams in multiple design centers across different time zones
- perform schematic-driven layout and design constraints
- design die-area efficient layouts according to circuit designer requirements
- perform block or top-level layout designs
- perform floor-planning, power line planning, shielding, and device-matching layout
- verify layouts and pass DRC, LVS, and ERC
- contribute to various chip-level routing and layout needs
- perform chip level integration, verifications, and tape-out
- support other projects as needed by management
Requirements
What you’ll need- BA/BS Degree in Layout Design or related field or equivalent experience
- 10 years’ experience with layout design for analog and full-custom digital blocks
- Experience TSMC 180nm, 65nm, 22nm process technologies
- Proficient in using layout editing tools in the Cadence Virtuoso design environment
- Solid working knowledge of debugging DRC/LVS/ERC with Cadence PVS or Mentor Calibre
- Conceptual understanding of layout topics such as parasitic, matching, crosstalk, transistor layout dependent effects, latch-up, IR drop, electro migration (EM), and deep N-well and NTN isolation
- Strong capability of solving device matching, electro-migration, signal integrity and power distribution problems while meeting area constraints
- Experience in chip – level floor planning and analog block integration
- Experience chip level integration, verifications, and tape-out
- Ability to use productivity – enhancing tools and design scripts to further automate tasks is also desirable
- Must be able to lift, push, and pull up to 5 lbs
Benefits
Comp & perks- comprehensive and highly competitive compensation package
- quarterly bonus tied to the achievement of innovation goals
- equity grants providing a meaningful opportunity to share in the company’s future growth and success
ATS Keywords
✓ Tailor your resumeApplicant Tracking System Keywords
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Hard Skills & Tools
CMOS circuitsBiCMOS circuitslayout designschematic-driven layoutfloor-planningpower line planningshieldingdevice-matching layoutDRCLVS
Soft Skills
leadershiptrainingcoordinationcommunicationproblem-solving
Certifications
BA/BS Degree in Layout Design