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About the role
Key responsibilities & impact- The Sr. Layout Design Engineer will lead top-level chip-planning and perform block-level custom layouts for CMOS and BiCMOS circuits.
- Review, and coordinate work content performed by offshore layout designers.
- Train junior layout engineers and offshore layout contractors.
- Contribute to developing standard layout methodologies across sites.
- Contribute to build process and procedures to achieve high layout quality.
- Requires remote interfacing with local and global design and layout teams in multiple design centers across different time zones.
- Lead Top-level chip-planning and perform functional-block-level, block-level, sub-block level, leaf cell, standard cell custom layouts for CMOS and BiCMOS circuits.
- Perform schematic-driven layout and design constraints.
- Design die-area efficient layouts according to circuit designer requirements.
- Perform block or top-level layout designs.
- Perform floor-planning, power line planning, shielding, and device-matching layout.
- Verify layouts. Pass DRC, LVS, and ERC.
- Contribute to various chip-level routing and layout needs.
- Perform chip level integration, verifications, and tape-out.
- Support other projects as needed by management.
- Contribute to developing common best practices and workflow across all sites.
- Contribute to build process and procedures to achieve high layout quality.
Requirements
What you’ll need- BA/BS Degree in Layout Design or related field or equivalent experience
- 10 years’ experience with layout design for analog and full-custom digital blocks
- Experience TSMC 180nm, 65nm, 22nm process technologies
- Proficient in using layout editing tools in the Cadence Virtuoso design environment
- Solid working knowledge of debugging DRC/LVS/ERC with Cadence PVS or Mentor Calibre
- Conceptual understanding of layout topics such as parasitic, matching, crosstalk, transistor layout dependent effects, latch-up, IR drop, electro migration (EM), and deep N-well and NTN isolation
- Strong capability of solving device matching, electro-migration, signal integrity and power distribution problems while meeting area constraints
- Experience in chip-level floor planning and analog block integration.
- Experience chip level integration, verifications, and tape-out.
- Ability to use productivity-enhancing tools and design scripts to further automate tasks is also desirable.
- Must be able to lift, push, and pull up to 5 lbs.
Benefits
Comp & perks- At SiTime, we believe great work deserves great rewards.
- We offer a comprehensive and highly competitive compensation package designed to attract top talent.
- In addition to base salary, this role is eligible for a quarterly bonus tied to the achievement of innovation goals—reflecting our commitment to recognizing meaningful impact.
- We also offer equity grants, providing a meaningful opportunity to share in the company’s future growth and success.
- SiTime is an Equal Opportunity Employer.
- We treat each person fairly and we do not tolerate discrimination or harassment against anyone on the basis of any protected characteristics.
ATS Keywords
✓ Tailor your resumeApplicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard Skills & Tools
layout designCMOS circuitsBiCMOS circuitsschematic-driven layoutfloor-planningpower line planningDRCLVSERCchip-level integration
Soft Skills
leadershiptrainingcoordinationcommunicationproblem-solving