Intel Corporation

DevOps Engineer

• Plan, manage, and optimize installation, configuration, and tuning NAS, S3, and backup solutions.
• Design and implement scalable storage and backup infrastructure modifications.
• Develop and enforce policies for consistent provisioning, uptime, and data protection.
• Track storage and backup usage, manage data migrations, and enhance configurations.
• Monitor performance and troubleshoot issues to maintain data integrity.

HPC Storage Dev Ops Engineer

Full-stack Engineer

• Develop cutting-edge software features and optimizations for Intel's communication libraries
• Design, develop, and maintain advanced features and performance optimizations for oneCCL
• Collaborate with scientists and engineers on high-performance computing applications
• Conduct comprehensive performance analysis and benchmarking
• Debug complex problems across multiple layers of hardware and software stack

Senior Cloud Software Development Engineer

• Develop sophisticated GenAI solutions using supervised/unsupervised learning, deep learning, reinforcement learning, and Bayesian analysis
• Work directly with users to define requirements for breakthrough products and solutions
• Translate ML models into production software through programming, testing, debugging, documentation, and deployment
• Fine-tune GenAI workloads for edge devices using xPU accelerators
• Support partners in GenAI workflow design and deployment

Senior GenAI Software Architect

Engineer

• Work on formal verification of Intel CPU design
• Acquire deep architectural and micro-architectural understanding of high complexity hardware design blocks
• Master state of the art Formal Verification techniques
• Develop verification collaterals in System Verilog
• Deploy new techniques in the large development team and work closely with tool and technology developers for problem solving

Formal Verification Engineer

• Develop ESD/LU rule decks aligned with the ESD Design Rule Manual (DRM).
• Create and maintain reliability ESD and LU design rule methodologies and specifications.
• Collaborate with internal design, reliability, and CAD teams as well as external EDA vendors.
• Build and execute test cases for rule debugging, validation, and signoff.
• Define QA requirements and drive related automation to improve robustness and efficiency of rule checks.

Senior EDA Tools Engineer – ESD

• Develop and test operating system components and runtime features for Intel's future neuromorphic products and evaluation platforms.
• Support bring-up, debug, and validation of prototype chips and platforms.
• Implement performance tuning and scaling of customer workloads.
• Develop automated test and validation frameworks for seamless deployment of Loihi systems and software to end customers.

Systems Software Engineer – Neuromorphic Computing

Mechanical Engineer

• Model, prototype, and document new features for improving product KPIs and expanding workload breadth. Evaluate tradeoffs in partnership with architects and algorithms researchers.
• Evaluate, select, and integrate vendor IP especially for chip/chiplet interfaces.
• Enter RTL and asynchronous design (CSP/CAST) optimized for synthesis and place-and-route closure.
• Work with system software developers and architects to define runtime, boot, reset, and power management modes and requirements.
• Review test plans and work with verification engineers to debug regression/test failures.
• Work with physical design engineers on floorplans, timing constraints, and post-layout timing issues.

Neuromorphic Silicon Design Engineer

• Develops the logic design, register transfer level (RTL) coding, and simulation for an SoC design
• Integrates logic of IP blocks and subsystems into a full chip SoC or discrete component design
• Participates in the definition of architecture and microarchitecture features of the block being designed
• Performs quality checks in various logic design aspects ranging from RTL to timing/power convergence
• Writes RTL and optimizes logic to qualify the design to meet power, performance, area, and timing goals
• Reviews the verification plan and implementation to ensure design features are verified correctly
• Works with IP providers to integrate and validate IPs at the SoC level
• Drives quality assurance compliance for smooth IPSoC handoff

Design Engineer – AI SoC Development

Solutions Engineer

• Understand client business processes and requirements to design a tailored Workday solution.
• Develop a comprehensive Workday architecture, including module selection, data mapping, and integrations with other systems.
• Configure Workday system settings, workflows, and security roles to match client specifications.
• Guide clients through project phases like discovery, design, configuration, testing, and deployment.
• Provide expert advice on Workday features, functionalities, and best practices to optimize system usage.
• Create training materials and user guides for end-users and administrators to ensure proper system adoption.
• Collaborate with cross-functional teams including sales, implementation consultants, and client stakeholders to manage project expectations.
• Identify areas for improvement within Workday implementations and propose solutions to enhance system efficiency.

Workday Solution Architect – Contract

Account Manager

• Join Altera as a Sales Account Manager managing sales budget targets
• Grow existing business within assigned accounts and uncover new business
• Drive all sales activities including demand creation, opportunity development, forecasting
• Manage issue resolution through collaboration with marketing, operations, applications engineering, and other supporting roles

Sales Account Manager

• Participate in design development tasks throughout the IP development flow.
• Develops the logic design, register transfer level (RTL) coding, and simulation for an IP.
• Applies various strategies, tools, and methods to write RTL and optimize the logic to quality the design to meet the IP release requirement.
• Involve in design example creation, simulation example creation, IP integration and release process.
• Involve in IP design example brings up on hardware, hardware verification and failure debugging.

Principal Logic Design Engineer

Sales Engineer

• Own and achieve sales targets for metrics such as new opportunities, design wins, and revenue growth within your territory.
• Drive all sales activities at focus, emerging, and major accounts, including demand creation, opportunity development, forecasting, pipeline management, and execution.
• Partner with distribution partners to enable success at focus and emerging accounts through training, joint customer visits, promotional activities, and strong collaboration.
• Directly manage and grow relationships at major accounts to expand Altera’s footprint.
• Ensure visibility of opportunities internally and accelerate technical support by collaborating with marketing, operations, applications engineering, and other teams.
• Represent Altera at customer meetings and local events to strengthen our presence and influence in the market.

Field Sales Engineer

• Participate in design development tasks throughout the IP development flow.
• Develop the logic design, register transfer level (RTL) coding, and simulation for an IP.
• Develops the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs.
• Applies various strategies, tools, and methods to write RTL and optimize the logic to quality the design to meet the IP release requirement.
• Involve in design example creation, simulation example creation, IP integration and release process.
• Involve in IP design example brings up on hardware, hardware verification and failure debugging.

Senior Staff Logic Design Engineer

• Develops the logic design, register transfer level (RTL) coding, simulation, and integrates the compute IP block for AI SoCs at the full-chip level.
• Participates in the definition of architecture and microarchitecture features of the block being designed.
• Qualifies the design through static design quality checks like lint, CDC, RDC, etc.
• Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, timing goals, and design integrity for physical implementation.
• Reviews the verification plan and implementation to ensure design features are verified correctly across verification hierarchies.
• Drives unit level verification, resolves and implements corrective measures for failing RTL tests to ensure correctness of features.

SOC Design Engineer

• Lead and inspire a team of world-class engineers developing next-generation optical components for data centers and emerging applications.
• Shape Intel’s technology roadmap by influencing product architectures and defining future photonic solutions.
• Drive cutting-edge design of 112Gbaud+ photonic components, including high-speed modulators, advanced detectors, phase controllers, and next-gen active/passive devices.
• Collaborate cross-functionally to ensure seamless integration across design, performance, reliability, yield, and certification with Intel and Intel Foundry partners.
• Deliver breakthrough photonic components that redefine performance and scalability.
• Set technical direction for Intel’s silicon photonics strategy.
• Lead innovation at the intersection of photonics, packaging, and system integration