Analog Layout Design Engineer

Intel Corporation

Analog Layout Design Engineer designing complex layouts for analog circuits at Intel. Collaborating with teams to drive innovative solutions and optimize designs for performance and reliability.

Posted 7/30/2026full-timeHillsboro • Oregon, Texas • 🇺🇸 United StatesMid-LevelSenior💰 $122,440 - $172,860 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in designing complex analog signal circuits and conducting thorough design verification checks. Proficient in troubleshooting layout-related issues and collaborating with cross-functional teams to ensure adherence to design specifications.

Highest-signal resume keywords

Analog Device FundamentalsCadence Virtuoso Layout SuiteCalibre/ICV DRCCMOS TechnologiesFloor Planning

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Analog Signal Circuit DesignDesign Verification ChecksVoltage Drop AssessmentPower Grid AnalysisHierarchical Layout PlanningLayout DebuggingMismatch UnderstandingParasitics AnalysisIR Drop AnalysisLVS Correlation

Soft Skills

CollaborationTroubleshooting

Industry Keywords

Electrical EngineeringComputer EngineeringMixed-Signal BlocksDesign SpecificationsLayout Effects

About the role

Key responsibilities & impact

Design complex layouts of analog signal circuits
Conduct design verification checks including process design rules and voltage drop assessments
Develop and analyze floorplans and power grids
Collaborate with cross-functional teams to meet design specifications
Troubleshoot issues related to design and methodologies

Requirements

What you’ll need

Bachelor's degree or equivalent experience in Electrical Engineering, Computer Engineering, or related field with 3+ years of experience
Analog device and metal layout fundamentals
Cadence Virtuoso Layout Suite and Calibre/ICV DRC for design and verification tasks
CMOS technologies and high-voltage rules
Floor planning and hierarchical layout planning for analog and mixed-signal blocks
Must have strong understanding of analog layout effects including mismatch, parasitics, and IR drop
Debug layout-related issues by correlating LVS, DRC, xtract, and silicon behavior

Benefits

Comp & perks

Health insurance
Retirement plans
Paid time off
Flexible work arrangements
Professional development
Stock bonuses