Marvell Technology

Security Engineer

• Define and articulate Marvell’s enterprise Product Security vision, strategy, and priorities in a clear and compelling manner.
• Communicate product security risk, trends, and recommendations to executive leadership in business-relevant terms.
• Prepare and deliver executive-level presentations that enable informed risk and investment decisions.
• Establish trusted relationships with senior leaders across engineering, product, legal, and operations.
• Own the enterprise Product Security strategy and multi-year roadmap spanning all product lines.
• Establish company-wide product security policies, standards, and governance models applied consistently across organizations.
• Drive alignment and accountability for security outcomes through partnership and influence.
• Partner closely with engineering, architecture, product management, quality, legal, supply chain, and operations teams.
• Enable teams to integrate security-by-design practices through guidance, tooling, and shared accountability.
• Act as a connector across organizations to resolve security issues that span multiple teams or products.
• Establish an enterprise product security risk management framework that enables consistent identification, prioritization, and treatment of risk.
• Translate technical vulnerabilities and architectural risks into clear business and customer impact assessments.
• Support executive decision-making by framing risk tradeoffs, mitigation options, and residual risk acceptance.
• Provide ongoing visibility into enterprise risk posture, emerging threats, and systemic issues.
• Serve as the executive owner of Marvell’s Product Security Incident Response Team (PCIRT).
• Lead cross-functional response to significant product security incidents, including executive briefings and customer communications.
• Oversee coordinated vulnerability disclosure and engagement with external researchers, customers, and partners.
• Ensure consistent, accurate, and timely security communications during incidents.
• Build and lead a core product security and PCIRT leadership team while operating within a federated model.
• Develop security champions and trusted partnerships across engineering organizations.
• Foster a culture of transparency, accountability, and proactive risk management across Marvell.

Senior Director, Product Security

Business Operations

• Generate and maintain product P&L through the quotation process
• Collaborate with the broader CCS team to refine and document internal processes
• Drive cross-functional teams to provide quality, well-documented inputs to the quote and forecast processes in a timely manner
• Identify process inefficiencies and work collaboratively with cross-functional teams to drive improvements

Business Operations Analyst – Demand Forecast, Supply Chain Management

Full-stack Engineer

• Define the sub system architecture, micro-architecture and register specification for highly complex SoCs
• Drive and participate in specification writeup
• Conduct detailed performance, architectural and design requirement reviews with cross-functional teams, IP Vendors and customers
• Implement a specification using RTL coding techniques and best practices
• Work with third party vendors to define customization requirements of third party IPs
• Work with the physical design teams, reviewing and providing guidance in floorplanning, power analysis, synthesis and timing signoff
• Work with the verification team on pre-silicon verification tasks such as reviewing the verification test plans, coverage analysis, full-chip simulation and emulation, performance and power analysis and debug
• Help develop and/or evaluate design and verification methodologies and participate in improving existing ones
• Collaborate with and provide guidance to the post silicon and software teams for silicon bring up and performance tuning
• Provide mentorship to the more junior team members

Senior Principal Engineer – RTL Design

Product Manager

• Own the internal coordination and prioritization process for the CCS BU
• Ensure cross-Marvell alignment on IP investments
• Monitor the ongoing success of projects
• Work with stakeholders across Marvell to define and maintain an IP roadmap
• Represent CCS BU in roadmap definition and change control discussions
• Help define technical and schedule requirements and monitor execution to commitments

Principal Product Manager – Custom Cloud Solutions, Silicon/Semiconductor IP

Consultant

• Own the operating model for executive compensation governance
• Enable disciplined planning for Compensation Committee meetings, regulatory disclosures, and annual filings
• Own the annual calendar for executive compensation, including Compensation Committee planning materials and key filing milestones
• Develop presentation materials, tracking deliverables, and coordinating with internal stakeholders and external consultants
• Support research and preparation for shareholder engagement meetings, focusing on executive compensation topics
• Establish clear decision frameworks, templates, and documentation standards for executive compensation decisions
• Track key decisions, follow-ups, and approvals to ensure governance continuity and audit readiness
• Build and maintain Excel-based models and analyses to support executive pay decisions

Senior Executive Compensation Consultant

Human Resources

• Assist with the onboarding program and new hire orientation, including coordinating guest speakers, managing communications, supporting I-9 completion, and other related tasks to ensure a smooth and positive experience for new employees.
• Respond to employee questions via ServiceNow or email regarding HR topics, issues, or status updates, applying best practices and following established response guidelines.
• Analyze incoming HR tickets to identify trends and opportunities for improving categorization and overall service delivery.
• Collaborate with the team to suggest enhancements to processes and contribute to better employee experience.
• Support projects involving third-party vendors, including the secure transition of employee records to an off-site vendor, gaining exposure to vendor management and project coordination.
• Contribute to special projects as needed, working alongside team members and stakeholders to gain broad exposure to HR operations.

HR Operations Intern

• Working on analog design for high-speed and high performance SerDes development in advanced technology nodes (5nm, 3nm, 2nm and beyond)
• Participate in SerDes Architecture Development with DSP, Analog and Digital design teams
• Provide instructions to the layout engineers
• Working with the AE for the IP characterization and validation

Senior Engineer, Analog IC Design

SDET

• Designing, debugging and correlating ATE HW and SW
• Develop ATE test programs for cutting edge high speed 400G optical PHY, Switch and large high-power compute AI products
• Receive a focused 3-month on-site Marvell ATE Test Engineering training in Irvine, CA
• Deployed working alongside our teams and their hiring managers at one of our standard Ops Engineering Sites across the globe

Test Engineer

Designer

• Active-circuit design
• Design of high-performance broadband analog and mixed-signal circuits for electrical and optical receiver front ends
• Design of various other analog circuits including linear regulators, AGC loops, current/voltage sensors, bandgaps etc.
• Work with other functional groups to facilitate post-silicon validation, qualification, transition to mass production, and customer support

Senior Staff Analog Mixed-Signal Design – Optical

• Active-circuit design.
• Design of leading edge transimpedance amplifiers, using both SiGe BiCMOS and the most advanced CMOS FinFET technologies, where circuit performance will need to transcend beyond industry leading products.
• Development of transmission line structures and other millimeter wave structures to enable higher performance than would normally be achievable.
• Design of high-performance broadband analog circuits for optical front-end receivers.
• Design of various other analog circuits including linear regulators, AGC loops, current/voltage sensors, bandgaps etc.
• Work with other functional groups to facilitate post-silicon validation, qualification, transition to mass production, and customer support.

Staff Analog Mixed-Signal Design – Optical

Hardware Engineer

• Develop and maintain embedded firmware for advanced hardware platforms, including data center, AI devices, SSD controllers, DSP networking chips, and high-speed PAM4 DSPs.
• Design and implement device drivers and firmware features for communication protocols (SPI, I2C, I3C, UART, MDIO, PCIe, NVMe) and RTOS-based systems.
• Participate in full product lifecycle : concept, design, implementation, testing, validation, and release to customers.
• Create and enhance automation scripts (Python, shell, bash) for testing, failure analysis workflows, and infrastructure management.
• Develop provisioning software and trusted firmware stacks to enable advanced security features for SoCs, including cryptography and secure protocols (TLS/SSL, IPSec).
• Collaborate with cross-functional teams (Hardware, System, QA, Customer Solutions) for integration, debugging, and performance optimization.
• Design and execute unit, system, and integration tests , including regression planning and continuous integration (Jenkins).
• Support lab testing and data analysis , including tool development for debugging, proof-of-concept preparation, and customer documentation.
• Work on mission-critical features for top-tier cloud customers and gain exposure to DSP concepts (Equalizers, Filters) and networking fundamentals (Ethernet, TCP/IP, OSI model).
• Debug complex hardware/software issues , drive root cause analysis, and manage fixes through issue tracking systems (e.g., Jira).

Firmware Engineer Intern

Financial Planning and Analysis

• Dive deep into financial data, performance metrics, and key performance indicators (KPIs) to uncover trends and insights that will drive our success
• Craft and present financial reports that tell a compelling story, including monthly, quarterly, and annual financial statements, along with variance analyses
• Collaborate with cross-functional teams to shape our annual budgeting process
• Develop and manage financial models that empower us to forecast accurately and perform scenario analysis on Opex, Capex, and Headcount
• Keep a watchful eye on budget vs. actual performance, providing strategic recommendations for adjustments
• Be part of our drive to optimize manufacturing and operational expenses through detailed cost analysis
• Evaluate product costs, pricing strategies, and profitability to ensure our competitive edge
• Utilize your financial acumen and Excel skills to develop robust models that calculate key performance indicators such as payback, NPV, IRR, and ROI, enabling comprehensive evaluation of project feasibility and long-term value
• Collaborate with cross-functional teams to gather and validate critical inputs—including R&D expenditures and detailed cost modeling data—to ensure accuracy and reliability in your financial assessments
• Dive into exciting ad hoc financial analysis projects and deliver insights that will shape our strategic direction

Financial Analyst

• Technically hands-on contributions along with mentoring and leadership for processor-based SoCs in Automotive/Server/Video/5G product space
• Work with multiple stakeholders across geographies for SoC DV ownership
• TB architecture definition and implementation
• creation, implementation and execution of test-plan (feature/performance/etc. aspects) sub-system and SoC level for a robust silicon tape-out sign-off
• contribute to in-house VIP creation for re-use across programs
• own 3rd party VIP integration
• participate with critical DV-oriented inputs in chip architecture discussions, design specifications and reviews, emulation plan reviews and DFT as well as PD relevant DV activities (DFT DV, Gate-level simulations, etc.)
• ensure end-to-end successful implementation of the IPs as well as Full-chip integration leading up to timely high quality tape-out
• Own/participate in key Verification methodology initiatives with impact across multiple programs towards improved execution efficiency and zero-defect silicon outcome

Design Verification Principal Engineer – SOC

• SI/PI analysis of designs and optimization of 2D/2.5D/3D packages
• interfacing with product design teams for optimized floor-planning, package related design input and power delivery network design
• perform wiring studies in order to determine optimal signal routing, power delivery verification and package size determination

Senior Engineer, Advanced Packaging SI/PI

Software Engineer

• Design, implementation, and maintenance of Linux device drivers and debug utilities for ARM64 based SoCs
• Participate in all phases of development and support including architecture, requirements, design, coding, unit testing, benchmarking, and support
• Work closely with the Hardware, Firmware, and internal test teams on resolving issues during unit and integration testing
• Contribute meaningfully to the Linux upstream community and OS distro vendors (such as RedHat and SUSE)