Marvell Technology

Program Manager

• Lead custom solution programs for hyperscale cloud data center customers
• Own the complete program lifecycle: initiation, planning, execution, and closure
• Drive execution across development, validation, qualification, sample delivery, and production release phases
• Monitor and control program performance to maintain alignment with schedule, quality, and cost targets
• Collaborate across a matrixed organization
• Serve as the primary point of contact for internal and external communications
• Proactively identify risks and lead mitigation planning
• Escalate and resolve issues effectively to maintain program momentum

Principal Program Manager – Hyperscaler Cloud Data Center, Full Lifecycle Program Ownership

Business Operations

• Set up and maintenance of collaborative workspaces
• Generation and maintenance of part numbers
• Collaborate with the broader CCS team to document internal processes
• Facilitate data entry and retrieval for weekly reporting cycles
• Help facilitate seamless data transmission from quote to forecast

Business Operations Analyst

Director

• Build, lead, and grow a verification and emulation engineering team in India, owning hiring, mentoring, and retention from day one
• Collaborate with US-based architecture, design, and verification leads to develop verification strategies for complex SoCs, chiplets, and multi-generation product roadmaps
• Own the verification of complex systems end-to-end—from verification planning through coverage closure and tapeout
• Drive the technical direction of the team: developing innovative verification strategies, maintaining high-quality code standards, and pushing the state of the art in methodology and automation
• Develop and maintain long-term verification plans spanning multiple product generations
• Own schedules, define progress metrics, and provide clear visibility into execution status across sites
• Provide hands-on technical mentorship, actively identifying improvements in methodologies, techniques, and infrastructure
• Partner with software and emulation teams to enable HW-SW co-development and accelerate silicon validation
• Lead DV, emulation and post silicon validation execution with zero defect mindset.
• Define DV, emulation and post silicon validation scope.
• Define execution timelines working closely with stakeholders.
• Set goals, monitor, and take steps to keep the execution on track.
• Define DV methodology and verification strategies.
• Drive definition and implementation of DV TB architectures.
• Collaborate with Architecture, Design, DFT, PD, FW and system teams for successful product execution.
• Lead tool evaluation and selection.
• Drive continuous productivity improvements through incremental and forklift changes.
• Monitoring industry DV trends and adapting to key trends.
• Hire, build and retain high performance engineering team.
• Address continuous training and development needs of the team.

Director, Design Verification

Designer

• Define and drive comprehensive verification strategies and test plans for complex SoCs, subsystems, or IP blocks in custom AI accelerators, CPUs, or high-speed interconnect silicon built in advanced process nodes (3nm, 2nm)
• Architect and implement sophisticated UVM-based verification environments including testbenches, reference models, scoreboards, monitors, coverage models, and protocol checkers to ensure exhaustive verification of assigned blocks
• Develop and execute comprehensive test plans encompassing directed tests, constrained-random scenarios, and coverage-driven verification to verify functional correctness, performance requirements, and error handling across all design features
• Own end-to-end verification closure including code coverage, functional coverage, and assertion coverage analysis, working with design teams to resolve coverage gaps and achieve 100% coverage goals with documented waivers
• Debug complex simulation failures using systematic root-cause analysis techniques, correlating RTL behavior with specifications, and partnering with designers to identify and resolve design issues efficiently
• Collaborate closely with logic designers, architects, DFT engineers, and physical design teams throughout the development cycle on micro-architecture reviews, test plan development, timing closure support, and gate-level simulation execution
• Drive verification methodology improvements by developing reusable verification components (VKITs), creating automation scripts for regression management and coverage analysis, and establishing best practices that enhance productivity across global verification teams
• Support multiple verification platforms including RTL simulation, emulation/FPGA prototyping, and post-silicon validation, ensuring test portability and maintaining verification infrastructure across platforms
• Integrate and validate third-party VIPs (Verification IP) and vendor models for industry-standard protocols, ensuring proper configuration and effective utilization within the verification environment
• Present verification progress, coverage results, and quality metrics to stakeholders through milestone reviews, cross-functional design reviews, and verification sign-off meetings, maintaining clear documentation throughout the verification cycle
• Coach and mentor junior verification engineers when necessary to develop their technical skills and achieve successful project outcomes

Senior Staff Design Verification Engineer

Principal Design Verification Engineer

Mechanical Engineer

• Define and drive micro-architecture and RTL implementation for complex functional blocks in custom AI accelerators, CPUs, or high-speed interconnect silicon, working in advanced process nodes (3nm, 2nm) to meet aggressive performance, power, and area (PPA) targets
• Own end-to-end delivery of assigned blocks or subsystems from architecture definition through tape-out, including synthesis, timing closure, formal verification, and physical verification sign-off
• Collaborate closely with cross-functional teams including verification engineers on test plan development and coverage analysis, physical design teams on floorplanning and timing optimization, and DFT teams on scan insertion and test pattern generation
• Drive timing and power closure for high-speed designs (>1 GHz), working with implementation teams to resolve congestion issues, develop timing ECOs, and optimize critical paths to achieve sign-off quality
• Partner with customer architects and engineers to translate application requirements into hardware specifications, participate in design reviews, and support technical discussions throughout the development cycle
• Integrate and validate third-party IP (PCIe, CXL, DDR, SerDes, etc.) within the SoC, ensuring interoperability and compliance with industry standards while meeting customer-specific performance requirements
• Support post-silicon validation and bring-up activities, including debugging silicon issues, correlating RTL simulations with lab measurements, and working with validation teams to resolve production issues
• Contribute to methodology development by improving design flows, developing automation scripts, and establishing best practices that enhance productivity across global design teams
• Present technical work and design trade-offs to stakeholders through design reviews, architecture discussions, and cross-functional team meetings, maintaining clear documentation throughout the development cycle

Principal Digital IC Design Engineer

Security Engineer

• Lead the development and evolution of Marvell’s enterprise security strategy.
• Provide advisory services and ensure the integration of security services.
• Communicate risk clearly, build strong partnerships, and influence direction across the enterprise.
• Serve as a primary integration point between technology teams, operations, solution engineering, and business stakeholders.
• Translate technical and operational risk into business impact, align diverse stakeholders, and drive decisive action through influence.

Director, Enterprise Security Architecture – Strategy

• Collaborate with the broader CCS team to ensure adherence to business processes
• Facilitate the timely delivery of critical system input and maintenance of internal systems
• Set up and maintenance of collaborative workspaces
• Generation and maintenance of part numbers
• Facilitate data entry and retrieval for weekly reporting cycles
• Help facilitate seamless data transmission from quote to forecast

Business Operations Staff

• Collaborating with various teams to develop strategies
• Pushing the IP roadmap and supporting multiple SoCs
• Provide leadership in the development of highest value-add IP & SoC plans
• Manage and continue to build a team of complex sub-system, co-processors, accelerator and SoC engineers
• Develop methodologies and infrastructure
• Work with architecture, SoCs, software, firmware, program management and post-silicon design teams for plan development and execution
• Provide technical mentoring for team members
• Actively engage in efforts to find improvements in methodologies, techniques, and automation

Senior Director – SoC Design

• Lead DV, emulation and post silicon validation execution with zero defect mindset
• Define DV, emulation and post silicon validation scope
• Define execution timelines working closely with stakeholders
• Set goals, monitor, and take steps to keep the execution on track
• Define DV methodology and verification strategies
• Drive definition and implementation of DV TB architectures
• Collaborate with Architecture, Design, DFT, PD, FW and system teams for successful product execution
• Lead tool evaluation and selection
• Drive continuous productivity improvements through incremental and forklift changes
• Monitoring industry DV trends and adapting to key trends
• Hire, build and retain high performance engineering team
• Address continuous training and development needs of the team

Senior Director – SoC Design Verification

Systems Engineer

• Develop behavioral and functional models of key SerDes and D2D DSP blocks
• Implement DSP algorithms and prototypes in C/C++, with Python for configuration, automation, and visualization
• Build parameterized system-level models to support architecture evaluation for SerDes up to 448G
• Perform simulation-level analysis across DSP, channel, and system blocks
• Correlate silicon/lab observations with system-model predictions to accelerate debug and refinement
• Work closely with other DSP engineers to convert conceptual ideas into executable C/C++ models
• Use system models to debug silicon performance gaps, timing issues, equalization behaviors, and adaptation anomalies
• Develop reusable C/C++ and Python modules for parameter sweeps, batch simulations, and data pipelines

DSP Systems Engineering – All Levels

• Seeking a Mixed Signal designer to be part of a key team designing highly sophisticated CMOS transceiver/SERDES products.
• Responsibilities would span architectural investigations and implementation for circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, CDRs etc. to meet key performance targets.
• Performing design verification using industry standard tools such as SPICE, Spectre, MATLAB etc.

Analog Mixed-Signal Design – All Levels

Hardware Engineer

• Transform system-level requirements into functional firmware
• Create documentation, including functional specifications, design documents, and test specifications
• Design and implement code unit testing processes
• Design and execute automated regression testing systems

Firmware Engineer

Financial Planning and Analysis

• Key stakeholder in the annual operating plan and long-range planning process across all business units
• Drive monthly and quarterly rolling forecast cycles, ensuring accuracy and business alignment
• Partner with business unit and support FP&A teams to consolidate enterprise P&L, balance sheet, and cash flow projections
• Develop and maintain financial models that support scenario analysis, sensitivity testing, and risk assessment
• Prepare and present quarterly earnings packages, and board materials
• Translate complex financial data into clear, concise narratives for the CFO, CEO, and Board of Directors
• Design and maintain executive dashboards and KPI scorecards that track performance against plan
• Act as a trusted financial advisor to functional leaders, providing data-driven insights and recommendations
• Partner with Accounting on close processes to ensure plan-to-actuals accuracy and variance resolution
• Champion automation and standardization initiatives to reduce cycle time and improve analytical capacity
• Foster a culture of intellectual curiosity, accountability, and cross-functional collaboration

Principal Financial Analyst – Corporate FP&A

Engineer

• Conduct feasibility modeling for next-generation cooling technologies, including phase-change systems, evaporative solutions, and immersion concepts.
• Evaluate early-stage cooling architectures in collaboration with silicon, mechanical, and test engineering teams.
• Perform thermal interface material (TIM) scouting, comparative research, and preliminary characterization.
• Translate future product power-density roadmaps into cooling performance requirements for early design phases.
• Lead end-to-end thermal and mechanical design of cooling assemblies, including thermal heads, manifolds, sockets, and fluid delivery structures.
• Execute full 3D thermal simulations, conjugate heat-transfer analysis, and transient thermal modeling to predict evaporator and cold-plate performance.
• Develop and validate TIM analysis.
• Own material selection and fluid-path design for high-flow cooling systems, ensuring stability, reliability, and manufacturability.
• Validate integrated thermal head + socket assemblies in the lab, including structural, thermal, and reliability characterization.
• Build reliability prediction models for thermal cycling, material fatigue, creep, and long-term system behavior.
• Develop multi-zone thermal control concepts, including sensor strategy, PID algorithm design, loop-tuning, and control-firmware interaction.
• Own TIM qualification workflows including thermal resistance measurement, mechanical endurance, and process compliance.
• Script automation sequences for calibration, system setup, thermal control routines, and ATE/handler interaction.
• Work closely with handler engineering teams to ensure seamless integration of thermal heads into ATE/SLT.
• Partner with silicon architects, packaging engineers, and electrical/mechanical design teams to ensure cooling compatibility and design alignment.
• Collaborate with reliability, manufacturing, and test engineering teams to define qualification plans and production-readiness criteria.
• Interface with external vendors for thermal head manufacturing, fluid system components, TIM suppliers, and advanced materials.