Intel Corporation

Full-stack Engineer

• Set up and maintain AI development environments on AI PC platforms (OS, drivers, frameworks, toolchains).
• Develop and experiment with Agentic AI systems, including multi step reasoning, tool usage, memory, and task orchestration.
• Explore and integrate new AI models and applications relevant to AI PC usage scenarios.
• Support pretraining and fine tuning methodologies, including data pipelines, training workflows, and model integration.
• Implement AI coding tasks across infrastructure and application layers to enable agent based workflows.
• Evaluate functionality, performance, and usability of agentic AI workloads on client platforms.
• Collaborate with cross functional teams on AI software enablement and HW/SW integration.
• Document experiments, design decisions, and best practices to support knowledge sharing and future scaling.

AI Software Engineering Intern

Mechanical Engineer

• Designs, develops, and builds analog circuits in advanced process nodes for analog and mixed-signal IPs.
• Designs floorplans, performs circuit design, extracts chip parameters, and simulates analog behavior models.
• Creates test plans to verify design according to circuit and block microarchitecture specifications and evaluates test results.
• Verifies functionality to optimize circuit for power, performance, area, timing, and yield goals.
• Collaborates cross-functionally to report design progress and collects, tracks, and resolves any performance and circuit design issues.
• Optimizes performance, power, area, and reduces leakage of circuits.
• Works with architecture and layout team to design circuit for best functionality, robustness, and electrical capabilities.
• As a principal engineer, recognized as a domain expert who influences and drives technical direction across Intel and industry.
• Develops and mentors other technical leaders, grows the community, acts as a change agent, and role models Intel values.
• Aligns organizational goals with technical vision, formulates technical strategy to deliver leadership solutions, and demonstrates a track record of relentless execution in bringing products and technologies to market.

Principal Analog Circuit Design Engineer – SerDes

Content Marketing Manager

• Publishing content on Intel Technology YouTube and X
• Driving content projects, including project management, coordinating with internal subject-matter experts and stakeholders, and collaborating with agency partners
• Engaging with the tech community through consistent, authentic, and transparent dialog on Intel Technology YouTube and X, along with Intel Insiders Discord
• Bringing the voice of the tech community into internal discussions
• Cultivating advocates and building relationships with tech enthusiasts and moderators
• Owning and executing Discord engagement activities
• Answering questions about Intel client products and technologies, and escalating cases to stakeholders and support teams where appropriate
• Providing occasional guidance to internal teams on social media and community responses that require additional technical and/or community nuance
• Collaborating on activities, programs, and strategies that drive education and advocacy in the tech community

Content and Community Specialist

Manager

• drive strategic growth and business development initiatives within Intel's Federal and Aerospace Division
• develop and execute comprehensive go-to-market strategies for federal and aerospace customers
• identify and analyze emerging opportunities in defense, aerospace, and civilian agencies
• create targeted market penetration plans for priority accounts and new customer acquisition
• lead business case analysis for new opportunities
• collaborate with capture and proposal teams to develop winning strategies
• represent Intel at industry conferences, tradeshows, and government forums
• partner with Intel's go-to-market and sales organization to align on customer strategies

Market Development Manager

Program Manager

• Translate manufacturing and market dynamics into actionable strategies for materials planning, risk mitigation, and total cost optimization.
• Coordinate and monitor the acquisition of materials to support New Product Introduction (NPI) programs/projects and enable ramp readiness for transition to High Volume Manufacturing (HVM).
• Collaborate with suppliers to execute contractual requirements, drive performance improvements, optimize costs, and develop future operational strategies.
• Partner with cross-functional teams across project/program management, engineering, supply chain, and manufacturing to define customer demand and establish early raw materials requirements.
• Ensure bills of materials integrity, availability, cost, and quality objectives are set and achieved.
• Provide regular assessments/status updates to stakeholders at multiple levels and establish contingency plans to close gaps and mitigate risks effectively.
• Analyze complex data to design solutions for process optimization, leveraging advanced tools and systems to drive efficiencies across Intel's operations.
• Manage supplier relationships to ensure on-time delivery, cycle time performance, resolution of material escalations, liability settlements, and engineering change order closures.
• Drive forward-looking supply chain solutions that align with Intel's production requirements and business goals, balancing cost control and inventory health.

Materials Program Manager – MPM

• Develop layout design methodology for testchip development in next generation process nodes
• Work closely with Process Integration, Yield and QnR to define critical Design features for early tests
• Establish and maintain hierarchical layout design specifications for integration
• Build and execute tactical plans for hierarchical SOC layout design
• Drive all aspects of physical design convergence

Senior Testchip SoC Physical Design Engineer, Integration & Methodology

• Contribute to the design, implementation, and validation of advanced analog and mixed-signal circuits for high-speed (112G and 224G) SerDes applications
• Participate in the definition, design, and verification of high-performance analog blocks and subsystems
• Engage in technical discussions and contribute to design reviews
• Conduct post-silicon validation and performance optimization
• Provide guidance to layout engineers and mentor junior analog designers
• Collaborate across disciplines with system architects, digital designers, and layout teams
• Develop innovative designs as part of a highly experienced SerDes team focused on next-generation high-speed interconnect solutions

Senior Staff Analog Circuit Design Engineer – SerDes

Designer

• Lead and mentor a team of logic designers
• Drive design implementation from specification to silicon
• Coordinate cross-functional collaboration
• Ensure design quality and schedule adherence

Logic Design Team Lead

• Work at the forefront of packaging technologies essential for next-generation AI devices
• Collaborate with substrate suppliers worldwide to drive innovation and scalability
• Contribute to the deployment of EMIB-T, our next-generation advanced packaging substrate technology
• Lead efforts to qualify new capacity at advanced packaging suppliers, ensuring timely readiness to meet growing customer demand
• Collaborate closely with on-site supplier engineering teams and the US integration team to advance substrate building block technologies
• Monitor, optimize, and improve capacity in bottleneck processes by implementing strategies that reduce throughput time (TPT)
• Oversee schedules for product and test vehicle (TV) deliveries, proactively resolving issues to achieve aggressive on-time delivery (OTD) targets
• Conduct thorough analysis of substrate lead times, develop reduction roadmaps, and consistently meet quarterly lead time goals
• Ensure strict adherence to Process Control System (PCS) commitments by suppliers
• Partner with internal teams to design and execute new factory TV/product certification plans focused on yield improvement
• Develop and maintain detailed micro-schedules for new factory startups, including milestone tracking to ensure supplier compliance with startup timelines
• Lead qualification activities and monitor ramp indicators to guarantee smooth, incident-free production ramp-up of new capacity
• Influence strategic decision-making at supplier management levels

Senior Substrate Program Manager

• Develops the logic design, register transfer level (RTL) coding, and simulation for an SoC design
• Participates in the definition of architecture and microarchitecture features of the block being designed
• Performs quality checks in various logic design aspects ranging from RTL to timing/power convergence
• Applies various strategies, tools, and methods to write RTL and optimize logic to meet power, performance, area, and timing goals
• Works with IP providers to integrate and validate IPs at the SoC level

SoC Logic Design Engineer

• Optimize emerging AI inference workloads such as Large Language Models (LLMs) and Diffusion models on GPUs
• Develop and optimize graph-based compilation flows (e.g., MLIR/LLVM) for neural network workloads
• Write and tune performance-critical GPU kernels and runtime code in C++ or parallel programming languages
• Identify and resolve bottlenecks across compiler, runtime, and kernel layers
• Profile, benchmark, and characterize AI workloads to validate performance gains
• Collaborate with hardware, driver, and framework teams on hardware/software co-optimization

AI Software Development Engineer

Engineer

• Extract, process, and cleanse complex design datasets to ensure data integrity and accuracy
• Identify, analyze, and interpret patterns and trends in large design reports and datasets using statistical and predictive modeling techniques
• Develop and automate data analytics, validation, and reporting tools to streamline processes and increase efficiency
• Act as a liaison between foundry tech and customer engineering teams, gathering and translating design requirements into technical specifications for foundry
• Monitor data integration performance and quality control plans, suggesting improvements to enhance accuracy and efficiency
• Develop interactive and intuitive reports

DTCO Systems Analysis Engineer

Sales

• Drive cloud consumption revenue by increasing adoption and stickiness of Intel-based instances across AWS deployments
• Co-develop and execute joint Go-To-Market strategies with AWS field teams, ISVs, and Systems Integrators
• Serve as trusted advisor to senior executives and architects, articulating Intel's value proposition for AI and enterprise workloads
• Identify and qualify new co-sell opportunities through deep engagement with AWS Sales and Partner teams
• Lead regional collaboration efforts, ensuring high-profile joint sales opportunities are sourced and closed
• Align sales programs and marketing efforts with customer business objectives across the Intel/AWS partner ecosystem
• Provide field insights to Intel technical teams to shape future hardware and software roadmaps

Sales Development Manager – Team AWS

• Top-down SoC Floorplan activities like best IP placement for latency/area in collaboration with architects, partitioning, PG grid creation, multi-power domain planning, pin-cutting, bump-planning by working with package/platform.
• Estimate die-area and define optimal physical dimensions for SoC by including product costs like die-per-reticle, right technology selection/metal stack and reuse from different product family.
• Drive execution and supervise progress of smaller blocks or sub-systems influencing their physical placement, shape, and channel planning to help them achieve best area and convergence schedule.
• Plan short and long-term work schedule, understanding dependencies between different domains like top, block place and route.
• Collaborate with other stake holders like the clock design to deliver the physical block level floorplans for APR and with the power delivery team on tradeoffs for metal allocation for signal and power.
• Help drive methodologies, tools and best-known methods to streamline Floorplan Physical Design work to achieve best-in-class on schedule delivery.

Fullchip Floorplan Design Engineer

• Defines, develops, and performs functional validation for GPUs
• Applies various hardware and software level tools and techniques
• Reviews proposed design changes to assess impact
• Develops GPU validation methodologies and collaborations for design optimization
• Performs silicon debug to identify root causes of failures
• Tests interactions between various GPU features using validation infrastructure
• Develops post-silicon validation infrastructure
• Publishes GPU validation reports and communicates results
• Works with architecture, design, verification, board, platform, and manufacturing teams