Senior Testchip SoC Physical Design Engineer, Integration & Methodology

Intel Corporation

Senior Testchip SoC Physical Design Engineer developing physical design methodologies and SoC integration for next-gen semiconductor technologies. Collaborating with design, process, and manufacturing teams for high-quality solutions.

Posted 5/15/2026full-timeHillsboro • California, Oregon, Texas • 🇺🇸 United StatesSenior💰 $141,910 - $200,340 per yearWebsite

About the role

Key responsibilities & impact

Develop layout design methodology for testchip development in next generation process nodes
Work closely with Process Integration, Yield and QnR to define critical Design features for early tests
Establish and maintain hierarchical layout design specifications for integration
Build and execute tactical plans for hierarchical SOC layout design
Drive all aspects of physical design convergence

Requirements

What you’ll need

Master's degree in electrical engineering or related field
Minimum of 5 years of experience in physical/layout design in advanced technology nodes
Proficiency in Layout design tools like Cadence Virtuoso Suite or Synopsys Custom Compiler
Knowledge of design rules and layout constraints in advanced semiconductor processes
Experience with floorplanning, hierarchical design integration, and layout verification/debug

Benefits

Comp & perks

Health insurance
Retirement plans
Paid time off
Flexible work arrangements
Professional development
Stock bonuses

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills & Tools

layout design methodologyphysical design convergencefloorplanninghierarchical design integrationlayout verificationlayout constraintsdesign rules

Certifications

Master's degree in electrical engineering