GlobalFoundries

Mechanical Engineer

• Responsible for developing and owning RTL development of AI-enabled RISC-V CPU core
• Drive the micro-architecture and design of critical blocks of the CPU core
• Design of RISC-V Vector CPU core and its custom extensions
• Design of AI-enabled Matrix engine to augment the Vector CPU
• Explore high-performance strategies working with the CPU modeling team
• Perform Microarchitecture development and specification from early high-level architectural exploration, through microarchitectural research to detailed specifications
• Configure Design Features Development, assessment, and refinement of RTL design to target power, performance, area, and timing goals
• Perform Functional verification support and assist in the design verification strategy
• Assist with the verification of RTL design performance goals
• Partner with a multi-functional engineering team to implement and validate physical design aspects of timing, area, reliability, testability, and power

Senior/Staff Design Engineer

Engineer

• Develop, deploy, and maintain PDKs (tech files, model files, rule decks, runtime code) for quantum devices and cryogenic control/readout ICs
• Create device libraries and parameterized cells (PCells), translating process design rules and SPICE/model specifications into design-ready implementations
• Support compact model development, parameter extraction, and correlation across TCAD, silicon data, and cryogenic characterization
• Integrate and validate PDKs within EDA environments (e.g., LVS/DRC, simulation flows), including development of automation tools representing fab processes
• Design test structures and test chips, and develop validation plans to ensure model accuracy and silicon correlation
• Develop and execute QA workflows, including DRC/LVS test cases and release validation, to ensure high-quality customer deliveries
• Analyze device and circuit data to identify variability, reliability risks, and performance trends; support yield-learning and root-cause analysis
• Create and maintain PDK documentation (release notes, application notes, known issues) and communicate usage guidance to users
• Collaborate cross-functionally with device, process, integration, and EDA teams to align design enablement with technology capabilities
• Contribute innovative ideas that may lead to intellectual property, patents, or advanced design enablement methodologies

Quantum PDK Engineer

• Support development of topological quantum devices and associated read-out and control circuitry
• Perform device physics analysis and modeling, with emphasis on low-temperature and cryogenic behavior of quantum devices.
• Develop and execute TCAD simulations to model device structures, materials interactions, electrostatics, and quantum transport effects.
• Design device layouts and test structures to support fabrication, characterization, and process development activities.
• Define and execute electrical characterization plans, including DC, RF, and cryogenic measurements, to evaluate device performance and variability.

Topological Qubit Device Engineer

Program Manager

• Lead end-to-end execution of strategic GF Labs programs from concept through program completion.
• Coordinate across device engineering, process integration, process engineering, advanced packaging, design enablement, and manufacturing as required to execute a program.
• Develop and maintain business cases GF Labs strategic programs.
• Partner with R&D finance and GF Labs technology teams to ensure budget alignment, cost tracking, and ROI transparency.
• Ensure external commitments are aligned with internal execution capability, schedules, and budgets.
• Identify and mitigate technical, schedule, manufacturing, and financial risks.

Quantum Technical Program Manager

Research Scientist

• Define and drive long-term technology roadmaps for topological qubits, including materials, device architectures, and integration strategies
• Lead development of topological quantum devices, with direct involvement in experiments, simulations, and prototype evaluation
• Work closely with device, integration, process, AME, PDK, and test teams to translate concepts into scalable semiconductor architectures
• Guide R&D of advanced materials, including III‑V heterostructures, epitaxy, superconductors, and topological material systems
• Contribute to experimental design, data analysis, and failure learning cycles for quantum devices
• Define system architectures linking qubits with cryogenic control and read-out electronics
• Drive modeling and validation strategies to improve coherence, performance, manufacturability, and scalability
• Translate device innovations into semiconductor-compatible integration approaches (BEOL, superconducting wiring, heterogeneous integration)
• Establish technical benchmarks, requirements, and success metrics aligned with internal and partner programs
• Serve as primary technical interface with customers and research partners to shape joint development efforts
• Lead and contribute to external collaborations, funded programs, and research proposals
• Communicate technical strategy, risks, and tradeoffs to leadership and multidisciplinary teams
• Mentor engineers and establish technical standards across topological quantum R&D

Quantum Topological Qubits Research Scientist

• Develop and optimize process modules including PVD, CVD, ALD, etch, and epitaxial growth (MBE, MOCVD)
• Engineer advanced materials systems including III‑V heterostructures, superconductors, and low-loss dielectrics
• Design and execute DOE experiments to evaluate materials, interfaces, and device performance drivers
• Characterize films using electrical, physical, and structural techniques to assess quality and variability
• Analyze data to identify key process drivers, defect mechanisms, and optimization opportunities
• Develop process recipes to meet device requirements, including cryogenic and low-noise performance
• Support integration of process modules into device and BEOL flows, including superconducting interconnects
• Collaborate with device and integration teams to align process behavior with device physics requirements
• Apply SPC and variability analysis to improve process stability, repeatability, and yield
• Support yield-learning and root-cause analysis activities
• Document process flows, results, and learnings for knowledge transfer and scale-up

Quantum Topological Qubit Manufacturing Engineer

Director

• Drive product line management for DSP/VPX business
• Oversee product lifecycle from concept through development to launch
• Lead initiatives to take customers to product stage for revenue realization
• Develop sales tools and training for internal teams and partners

Director of DSP/VPX Business

• Perform various tasks associated with Design Verification RISCV architecture Processors/Cores
• Reviewing Design and RISCV Standard Specifications
• Test Bench Development
• Test Plan Creation
• Tests Creation
• Test Case Debug
• Coverage Closure.
• Modeling, Flow and Methodology development

Experienced Staff Design Engineer, Verification

Artificial Intelligence

• Develop AI enablement strategies tailored for HR, Marketing, and Communications workflows
• Identify and prioritize high-impact use cases in forecasting, product, marketing, and planning
• Design and implement proof-of-concepts (POCs) and minimum viable products (MVPs) leveraging GenAI, ML, automation, agents, or other emerging technologies
• Collaborate with relevant business teams to understand their challenges, identify ideal AI-enabled business processes, and develop hands-on prototypes
• Create reusable playbooks, reference architectures, and enablement assets for business teams
• Collaborate with data platform and security teams to ensure secure and governed access to data for AI solutions
• Partner with business teams on change management initiatives, including training and communication for adoption
• Ensure compliance with Responsible AI principles and governance frameworks

AI Enablement Strategist – New College Graduate

Product Marketing

• Collects, analyzes and reports management data to support decisions on day-to-day operations, strategic planning and specific business performance issues and improvements.
• Uses data to obtain quantifiable economic benefit to accrue market share, revenue or cost savings (internal monetization).
• Collates, models, interprets and analyzes data; explains variances and trends.
• Identifies and documents enhancements to modeling techniques.
• Own product positioning, value propositions, and differentiation messaging for ULP CMOS / FDX platforms.
• Develop and maintain external-facing collateral aligned with GF messaging.
• Partner with Sales and Account Teams to support customer engagements, executive meetings, and key design wins.
• Act as a single-threaded owner across Product Management, Sales, Manufacturing, and Ops for business-level execution topics.

Product Marketing Manager

Attorney

• Proactively drive the strategy and develop the facts in support of GF’s substantive and procedural positions in third party patent assertion matters
• Negotiate with third party patent owners to resolve where possible litigation and pre-litigation assertions
• Partner closely with outside counsel to represent GF in such assertions; provide the necessary support to outside counsel to ensure that they can provide the best possible representation of GF and achieve cost effective and efficient successful results for GF
• Work in close collaboration with members of GF’s engineering, finance, sales, and market analysis teams in collecting and analyzing information relevant to such assertions
• Advise executive management on status and recommended options for such assertions

Senior Attorney, IP Law

• Design, build, and enhance FPGA and emulation platform solutions for single-core and multi-core clusters, integrating custom and 3rd party system IP as needed.
• Perform pre-silicon CPU and system validation using FPGA and hardware emulation platforms to ensure functional correctness and performance targets are met.
• Analyze system performance on FPGA platforms and help optimize for area and speed by effectively leveraging available FPGA resources.
• Drive the development of tailored FPGA prototyping platforms based on customer specifications and evolving project requirements.
• Collaborate closely with customer teams to enable rapid prototyping of their SoCs, supporting both hardware evaluation and software development needs.
• Develop, document, and execute pre-silicon validation test plans, including corner cases, integration scenarios, and debug strategies.
• Integrate, verify, and bring up daughter boards, custom IP, and peripheral modules in real-time device environments.
• Provide technical support and troubleshooting for FPGA systems in both customer-facing and internal R&D environments.

FPGA Prototype/Emulation Engineer

Product Manager

• Define and drive A&D requirements for CPU IP, multi-year roadmap, and portfolio strategy to the IP BU covering performance and certification requirements.
• Define and drive A&D requirements for Custom Silicon, multi-year roadmap, and portfolio strategy to the Custom Silicon Bub covering performance and certification requirements.
• Identify market opportunities across avionics, space, radar, secure communications, and embedded defense systems.
• Translate customer and regulatory requirements into clear product requirements and differentiated value propositions.
• Serve as the voice of the customer; engage directly with prime contractors, government customers, and ecosystem partners through Sales and respective BUs.
• Support Sales in customer pursuits, RFP/RFI responses, and technical positioning.
• Conduct competitive analysis and market sizing to guide investment decisions.
• Ensure products meet relevant standards (e.g., DO-254, ISO 26262 where applicable, safety/security frameworks, export controls).
• Partner with quality and compliance teams to support certification and customer audits.
• Develop positioning, messaging, and collateral for CPU IP offerings.
• Support pricing strategy, licensing models, and customer negotiations.
• Manage product lifecycle including obsolescence planning and long-term support strategies common in A&D programs.
• Work closely with CPU architects, silicon engineering, software teams, and program management.
• Influence without authority across global teams and external partners.
• Provide regular updates to executive leadership on product performance and market trends.

Product Manager – Custom Silicon

Designer

• Perform functional verification of CPU cores and related subsystems (coherency and cache controllers).
• Understand and interpret microarchitectural specifications to develop effective verification strategies.
• Develop and execute verification plans, including testbench creation and test case development.
• Write directed and constrained random test cases in SystemVerilog, C, and Assembly.
• Utilize UVM-based environments for coverage-driven verification.
• Analyze coverage reports and assist in closing coverage gaps.
• Automate regression and verification flows using scripting languages such as Python, Perl, or Shell.
• Collaborate with senior engineers and architects to ensure design quality and performance.