AI/ML Staff Software Engineer

GlobalFoundries

AI/ML Staff Software Engineer defining architecture strategy for AI/ML workloads in semiconductor industry. Collaborating across hardware and software to optimize performance and design.

Posted 6/11/2026full-timeRichardson • California, Texas • 🇺🇸 United StatesLead💰 $106,000 - $184,000 per yearWebsite

About the role

Key responsibilities & impact

Own workload characterization and hardware performance analysis for AI/ML systems — selecting representative workloads, defining measurement methodology, building support for MIPS products (e.g., the S8200), and projecting system-level KPIs.
Define the software frameworks across the product portfolio: what metrics matter, how to measure them accurately, how to estimate them pre-silicon, and how to use them to make architectural bets.
Leverage open-source infrastructure like MLIR and IREE to implement and validate this work.
Set the standard for how the team approaches this and mentor junior engineers in applying it.
Represent software in architectural discussions with hardware teams (CPU, SoC, memory, interconnect) and software teams (compilers, runtimes, ML frameworks).
Identify critical bottlenecks — compute throughput, DRAM bandwidth, on-chip memory, data movement latency, or software overhead — and build the case for specific architectural changes or optimization investments.
Present findings and recommendations to senior engineering leadership and product stakeholders.

Requirements

What you’ll need

BS or MS (preferred) in EE, CE, CS, or equivalent, with 5+ years in systems engineering, hardware architecture, ML systems, or performance engineering, and a track record of technical leadership.
Deep expertise in CPU and SoC architecture — memory hierarchies, out-of-order execution, vector/SIMD pipelines, power management — and how these interact with AI/ML workloads.
Strong command of system-level memory bandwidth constraints (DDR/LPDDR bandwidth, channel configuration, utilization efficiency) and the ability to reason quantitatively about memory-bound vs. compute-bound workloads.
Experience with AI/ML acceleration on edge devices — NPUs, dedicated inference accelerators, DSP-based pipelines — and the HW/SW co-design challenges involved.
Familiarity with model quantization, sparsity, or other efficiency techniques and their hardware interaction is a strong plus.
Familiarity with AI compiler infrastructure: MLIR-based toolchains, IREE, TVM, TFLite, or equivalent.
Understanding how graph representations are transformed, tiled, scheduled, and lowered to hardware will improve your ability to identify where compiler strategy and hardware architecture must be co-designed.
Prior contributions to such toolchains are a significant differentiator.
Effective cross-functional collaborator who can drive technical consensus without direct authority, writes clearly, and calibrates technical depth for different audiences.

Benefits

Comp & perks

Environmental, Health, Safety & Security requirements and programs

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills & Tools

workload characterizationhardware performance analysisAI/ML systemsCPU architectureSoC architecturememory hierarchiesout-of-order executionvector/SIMD pipelinesmemory bandwidth constraintsAI/ML acceleration

Soft Skills

technical leadershipmentoringcross-functional collaborationtechnical consensusclear writingcalibrating technical depth

Certifications

BS in EEBS in CEBS in CSMS in EEMS in CEMS in CS