Cadence Design Systems

QA Engineer

• Collaborate with IP design teams, methodology teams, CAD teams, and engineering management
• Ensure continuous improvement of processes and quality of product
• Analyze design defects to determine root causes
• Define design QA and release QC processes
• Maximize efficiency of processes through implementation of agentic AI systems
• Communicate quality metrics to senior engineering management
• Participate in quality certification activities for standards such as ISO 9001

Senior Principal Technical Quality Engineer

Software Engineer

• Contribute to the development, verification, validation, and deployment of advanced aeroelastic simulation capabilities.
• Work with senior technical staff to transition advanced research concepts into production-quality commercial software.
• Contribute to the development of simulation technologies for high-speed and hypersonic vehicle applications.
• Collaborate with structural dynamics, CFD, and multiphysics development teams to build integrated simulation workflows.
• Develop robust and scalable commercial software capabilities.

Computational Aeroelasticity Developer

Chief Technology Officer

• Maximize the value of Cadence solutions and flows
• Develop, lead, and close technical campaigns
• Introduce new technologies and methodologies
• Build strong relationships with customer engineers and leadership
• Collaborate with application engineers and sales executives

Digital IC, Account Technology Executive – ATX

Network Engineer

• Design and deliver scalable, resilient Data Center, Campus Network solutions using Cisco, Arista, HPE, and Aruba platforms.
• Support WAN operations such as internet edge, and SD-WAN integrations with consistent routing and security posture.
• Lead complex troubleshooting, root-cause analysis, and implement preventive changes to prevent incidents and unscheduled outages.
• Partner with various teams such as Data Center, Storage, Virtualization, Windows, Unix, Cloud Ops, and Security to provide technical direction and deliver cross-domain programs.
• Establish and maintain network documentation, diagrams, standards, and runbooks; ensure designs are supportable and operationally ready.
• Operationalize delivered solutions for Day 2 operations, including monitoring/alerting, capacity planning, lifecycle management, and change/release processes.
• Provide clear, timely status, risks, and tradeoffs to stakeholders; manage deliverables, timelines, and dependencies across multiple initiatives.

Staff Network Engineer

Mechanical Engineer

• Contribution during firmware architecture development and implementation of the defined firmware features.
• Working closely with verification team to debug and fix the FW issues found with verification simulations.
• Involvement during post-silicon testing and validation to identify any FW and HW related functionality and performance issues and implement any necessary FW improvements to address these issues.
• Interaction with Product Engineering, System Validation and Design team to debug IP issues in the field and provide hot fixes.
• Help to build system level prototype control software to develop/validate adaptation, equalization, and control algorithms for high speed SERDES.
• Implement assigned FW features and work closely with verification and validation team to ensure the functionality and robustness of the implemented features.
• Support of Validation team during electrical and system characterization.
• Support of Product Engineering team during customer deployment of the IP.

Firmware Design Engineer

Systems Engineer

• Be part of a hands‑on development team that promotes engineering excellence, creativity, and innovation
• Develop accurate, simulation‑efficient analog and mixed‑signal behavioral models (RNM) in SystemVerilog
• Verify that behavioral models accurately represent analog schematics and design intent
• Integrate analog behavioral models with RTL environments
• Verify analog and mixed‑signal functionality against specifications using SystemVerilog testbenches, test scenarios, and assertions, including Analog Assertion‑Based Verification
• Support verification of blocks such as filters, ADC/DAC, VCO, A/DPLL, SerDes, LNA, mixers, and related AMS IP
• Debug verification failures across analog, digital, and mixed‑signal domains
• Develop and maintain verification infrastructure including testbenches, environments, and scripts
• Document modeling assumptions, verification methodology, and results for formal design and verification reviews
• Collaborate cross‑functionally with design, systems, and IP teams to understand constraints and ensure verification coverage.

Mixed Signal Systems Engineer II

Principal

• Collaborate with prominent semiconductor and system companies to implement Cadence’s Jasper Formal Verification solutions.
• Provide hands-on technical support throughout both the pre-sale and post-sale stages.
• Deliver exceptional reactive support, proactive training, and expert consultation.
• Partner with R&D teams to introduce innovative formal flows and applications to customers.
• Advocate for customer needs and assist in the development of competitive and inventive solutions.
• Stay informed about the competitive landscape and seek ways to distinguish offerings.
• Mentor junior AE team members and foster a collaborative, team-oriented environment.
• Represent Cadence at technical conferences and trade shows.

Principal Jasper Formal Verification AE

Solutions Engineer

• Drive product and business growth for Cadence digital and mixed-signal verification solutions
• Own customer-facing strategy, market development, and go-to-market execution
• Partner directly with strategic accounts to uncover technical and commercial pain points
• Shape product direction and packaging
• Build compelling value propositions that accelerate adoption
• Align customers and internal teams around measurable outcomes
• Lead cross-functional initiatives across Sales, Applications Engineering, and R&D

Senior Principal Product Manager – Digital and Mixed Signal Verification Solutions

Collections

• Resolve client-billing problems and address accounts receivable delinquency, applying good customer service in a timely manner.
• Provide weekly and quarterly metrics reports with updates on collection status and analysis of movements on the accounts receivable ledger.
• Liaise with Order Management and Accounting teams to ensure correct cash application to customer accounts.
• Review open accounts receivable and engage in required collection efforts.
• Make outbound collection calls/emails in a professional manner while maintaining and improving customer relations.
• Manage customer software access in line with customer payments.
• Prepare cash flow forecasts for customer account portfolio including examination of existing and future billings and assessment of expected collection dates.
• Prepare various reports as required.
• Occasional project work.

Senior Credit & Collections Specialist

Account Executive

• Utilize technical knowledge to maximize value of Cadence solutions
• Build relationships with business and technology stakeholders
• Identify customer challenges and drive new business
• Collaborate with Cadence technical staff and customers
• Foster and grow customer relationships with key stakeholders

Data Center Account Technical Executive

• Implement, verify, and conduct timing closure to tape out Palladium and Protium SOCs
• Lead a team to implement SOCs or sub-system chips
• Work on RTL synthesis and floor planning
• Build clock trees and perform optimizations
• Close timing, IR drop and physical verification
• Review and document designs for taping out
• Interface with Front End RTL design teams and Back End Verification teams

Principal Design Engineer

• provide strategic leadership at the intersection of quantum, photonics, and electronic design automation
• engaging directly with customers to understand complex technical and business challenges
• defining high-impact solutions using Cadence technologies
• shaping project scope, deliverables, and investment requirements
• partner closely with services leadership and R&D to identify tool requirements
• influence future development priorities
• drive execution across extended internal and customer-facing teams
• advance Cadence’s quantronics capabilities by developing deep expertise

Solutions Architect

Hardware Engineer

• Develop firmware for DDR5 PHY using microcontrollers
• Developing firmware in C typically involving bare-metal programming
• Collaborating with hardware designers to derive training algorithms
• Collaborating with the verification team for firmware-hardware co-verification
• Develop and Debug firmware in RTL based hardware simulations
• Develop and Debug on Silicon bring-up boards

Lead Firmware Engineer

• Drive hands-on development and validation of Pegasus DRC and LVS runsets for advanced semiconductor nodes.
• Design, enhance, and maintain automation frameworks for regression execution, issue detection, and validation reporting.
• Collaborate closely with R&D and cross-functional teams to debug issues, validate fixes, and improve solution quality and performance.
• Provide technical enablement and support to customers on tool usage and advanced physical verification methodologies.
• Apply and help refine best practices for runset development, validation, and quality assurance.
• Work independently on complex technical deliverables while contributing knowledge and guidance within the team.
• Partner with internal teams to support predictable and timely delivery of physical verification solutions.

Lead Solutions Engineer – Runset Enablement, Physical Verification

• Participating in or leading next-generation physical design, methodology, and flow development in advanced technology nodes.
• Perform physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure.