Physical Design Engineer II – PNR, Physical Verification, STA, EMIR

Cadence Design Systems

Physical Design Engineer II working on advanced technology node designs. Engaging in physical design implementation and methodology development in semiconductor technology.

Posted 6/19/2026full-timeToronto • 🇨🇦 CanadaMid-LevelSeniorWebsite

ATS Keywords

Tailor your resume

Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard Skills

physical designfloor planningpower grid designplace and routeclock tree synthesistiming closurepower integritysignal integrityphysical verificationstatic timing analysis

Soft Skills

ability to learn quicklycarefulnessresponsibilitypersistence

Tools & Technologies

scripting languages

Industry Keywords

N7 processN5 processDRCDFMLVSANTERCEM signoffIR signofftiming closure

About the role

Key responsibilities & impact

Participating in or leading next-generation physical design, methodology, and flow development in advanced technology nodes.
Perform physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure.

Requirements

What you’ll need

Bachelor or above degree in majors of EE/CS/IT, with 3+ years work experience
Extensive knowledge of the design rule for the process of N7/N5 and below
Knowledge of scripting languages and use in methodology
Ability of fixing the physical design violations, including: DRC, DFM, LVS, ANT, ERC etc.
Deep experience of static timing analysis
Ability to learn quickly
Carefulness, responsibility, and persistence

Benefits

Comp & perks

Health insurance
Professional development opportunities