Principal Design Engineer

Cadence Design Systems

Principal Design Engineer implementing and verifying Palladium and Protium SOCs at Cadence. Leading teams and collaborating with design and verification teams to achieve project goals.

Posted 6/26/2026full-timeSan Jose • California • 🇺🇸 United StatesLead💰 $136,500 - $253,500 per yearWebsite

Tech Stack

Tools & technologies

LinuxPerl

About the role

Key responsibilities & impact

Implement, verify, and conduct timing closure to tape out Palladium and Protium SOCs
Lead a team to implement SOCs or sub-system chips
Work on RTL synthesis and floor planning
Build clock trees and perform optimizations
Close timing, IR drop and physical verification
Review and document designs for taping out
Interface with Front End RTL design teams and Back End Verification teams

Requirements

What you’ll need

BS degree in Electrical Engineering with a minimum of 7 years of experience OR MS with a minimum of 5 years of experience OR PhD with a minimum of 1 year of experience
Experience with Cadence tools such as Innovus, Tempus, QRC, Voltus and Pegasus
Experience with advanced technologies like 5nm, 3ns and 2nm nodes
Experience using Linux servers
Script development using Shell/Perl/TCL
Detailed knowledge about industry standard interfaces such as PCI Express, DDR, LPDDR, SRAM, UCIe, etc.

Benefits

Comp & perks

paid vacation and paid holidays
401(k) plan with employer match
employee stock purchase plan
a variety of medical, dental and vision plan options
flexible work arrangements
professional development opportunities

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills & Tools

RTL synthesisfloor planningtiming closureclock tree optimizationIR drop analysisphysical verificationscript developmentShell scriptingPerl scriptingTCL scripting

Soft Skills

leadershipteam collaborationdocumentation