Mixed Signal Systems Engineer II

Cadence Design Systems

Mixed-Signal Systems and Verification Engineer at Cadence developing verification for digital and mixed-signal designs. Collaborating with cross-functional teams to deliver high-quality silicon to market.

Posted 7/15/2026full-timeToronto • 🇨🇦 CanadaJunior💰 CA$73,500 - CA$136,500 per yearWebsite

Core Competencies

Role fit

Core Competencies

Use this summary to align your resume positioning with the role.

Demonstrates expertise in SystemVerilog for analog and mixed-signal behavioral modeling and verification, with a strong foundation in real-number modeling and analog block functionality. Capable of collaborating effectively across teams to ensure comprehensive verification coverage and documentation.

Highest-signal resume keywords

SystemVerilogAnalog and Mixed-Signal VerificationReal-Number Modeling (RNM)Cadence VirtuosoCommunication Skills

ATS Keywords

Tailor your resume

Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard Skills

Behavioral ModelingVerification MethodologyTestbench DevelopmentAnalog Assertion-Based VerificationDebuggingMixed-Signal FunctionalityAnalog BlocksDigital DesignSimulation EfficiencyDesign Intent Verification

Soft Skills

CollaborationWritten CommunicationVerbal Communication

Tools & Technologies

Cadence Virtuoso Schematic ComposerADESystemVerilog Testbenches

Certifications & Qualifications

Bachelor’s Degree in Electrical EngineeringMSEE or PhD Preferred

Industry Keywords

Analog DesignMixed-Signal DesignDigital DesignVerification EnvironmentsSignal ProcessingFiltersADCDACPLLSerDes

Tech Stack

Tools & technologies

DAC

About the role

Key responsibilities & impact

Be part of a hands‑on development team that promotes engineering excellence, creativity, and innovation
Develop accurate, simulation‑efficient analog and mixed‑signal behavioral models (RNM) in SystemVerilog
Verify that behavioral models accurately represent analog schematics and design intent
Integrate analog behavioral models with RTL environments
Verify analog and mixed‑signal functionality against specifications using SystemVerilog testbenches, test scenarios, and assertions, including Analog Assertion‑Based Verification
Support verification of blocks such as filters, ADC/DAC, VCO, A/DPLL, SerDes, LNA, mixers, and related AMS IP
Debug verification failures across analog, digital, and mixed‑signal domains
Develop and maintain verification infrastructure including testbenches, environments, and scripts
Document modeling assumptions, verification methodology, and results for formal design and verification reviews
Collaborate cross‑functionally with design, systems, and IP teams to understand constraints and ensure verification coverage.

Requirements

What you’ll need

0–2+ years of experience working in digital, analog, or mixed‑signal design and verification environments
Bachelor’s degree in Electrical Engineering or related field (MSEE or PhD preferred)
Strong understanding of SystemVerilog and mixed‑signal verification concepts
Experience or coursework in real‑number modeling (RNM) including: wreal, UDN, UDT, UDR, Verilog‑AMS
Basic understanding of analog and mixed‑signal blocks such as ADCs, DACs, PLLs, SerDes, RF or signal‑processing components
Familiarity with Cadence Virtuoso Schematic Composer and ADE
Strong written and verbal communication skills with the ability to work across teams
Comfortable working in a fast-paced, collaborative development environment.

Benefits

Comp & perks

Paid vacation and holidays
Leave of absence programs
Registered Retirement Savings Plan (RRSP)
Tax Free Savings (TFSA) plan for post-tax investment savings
Employee Stock Purchase Plan
Group health coverage that includes dental, vision, and Emotional Wellbeing Support (EAP) benefits for you and your eligible dependents
Life insurance for employees and dependents
Short-term and long-term disability coverage
Global Travel Medical coverage
Business Travel Accident Insurance
Funded Lifestyle Spending Account (LSA)