Marvell Technology

Designer

• Work on verification of Marvell's AI/ML, Network processing, Compute, Automotive, and Baseband SoCs and IPs
• Develop the architecture for a functional verification environment, including reference models and bus-functional monitors and drivers using System Verilog and UVM methodology
• Develop verification testplan and write tests using random techniques and coverage analysis
• Work with designers to ensure the verification is complete
• Develop tests and tune the environment to achieve coverage goals
• Debug failures and work with designers to resolve issues
• Architect, develop and maintain tools to streamline the design of state-of-the-art multicore SoCs
• Experience with analysis/closure of code and functional coverage

Principal Design Verification Engineer

Solutions Engineer

• Serve as the primary point of contact for FP&A systems architecture, design, support, and continuous improvement
• Partner with FP&A, Accounting, IT, and business teams to understand planning and reporting requirements and translate them into scalable system solutions
• Lead solution design for budgeting, forecasting, long-range planning, management reporting, and scenario modeling processes
• Drive architecture and roadmap decisions for FP&A platforms and related integrations
• Support and enhance enterprise performance management (EPM) platforms such as OneStream and related planning tools
• Define and improve end-to-end FP&A business processes, including data flows, hierarchies, metadata, and governance
• Work closely with business stakeholders to identify pain points, resolve system issues, and deliver long-term improvements
• Lead system configuration, business rule design, workflow setup, data mapping, and integration activities
• Partner with data and integration teams to ensure accurate and timely movement of data across ERP, data warehouse, and planning systems
• Ensure strong controls around data accuracy, system security, auditability, and process compliance
• Support month-end, quarter-end, annual planning cycles, and ad hoc business requests
• Drive automation and simplification opportunities to reduce manual effort and improve planning efficiency
• Provide functional leadership across testing, deployment, release management, and user adoption
• Create and maintain documentation for system design, process flows, business requirements, and support procedures
• Provide guidance on best practices in FP&A systems, planning processes, and solution design
• Engage with software vendors and implementation partners as needed to address product issues, upgrades, and new capabilities
• Stay current on emerging technologies, including AI and GenAI opportunities in finance processes, and identify practical use cases
• Partner with data science and engineering teams to productionize AI-enabled solutions with strong governance, accuracy, and explainability

FP&A Systems Principal Professional / Solution Architect

Full-stack Engineer

• Early involvement in NPI with focus on manufacturing process development
• Define and champion DfM requirements across cross-functional teams to ensure product scalability and reliability
• Own the transition of advanced optical designs into high-volume production; drive manufacturing readiness, characterization, and PFMEA
• Own overall yield roadmaps, cost analysis, and continuously yield improvement

Principal Product Engineer, Optics

• Design, operate, and continuously improve the engineering compute infrastructure for large-scale chip design and verification
• Own and evolve grid job management infrastructure used for large regressions and high-volume batch workloads
• Debug and resolve grid job failures, including scheduling issues, hung jobs, resource starvation, and intermittent infrastructure faults
• Improve job reliability through watchdogs, retries, heartbeats, timeouts, and failure detection mechanisms
• Develop deep operational understanding of shared engineering storage systems used by compute jobs
• Collaborate with IT teams on filesystem migrations, maintenance windows, and outage prevention
• Proactively identify systemic issues that lead to grid instability or job loss
• Act as a technical bridge between engineering users, tools teams, and central IT

Staff Engineer – Compute Infrastructure and Grid Operations

• Design, implement, and maintain chip design build flows supporting block, subsystem, full-chip, and multi-chip simulations.
• Develop and own build scripts and orchestration logic for compile, elaborate, simulate, and regression workflows.
• Improve build performance through dependency analysis, incremental builds, caching, and flow optimization.
• Define and evolve methodology standards for front-end design and verification flows.
• Architect and enhance CI / pre-submit verification flows to improve quality and turnaround time.
• Integrate and support industry EDA tools within robust scripted flows.
• Collaborate with RTL, DV, methodology, and infrastructure teams.
• Debug complex infrastructure and build-system issues.
• Drive adoption through documentation and training.

Senior Staff Engineer, Digital IC Build Flow – Methodology

• Own the packaging technology roadmap for AI XPU, XPU-attach and Switch
• Define system-level package architecture including chiplet topology, interposer/substrate scaling, power delivery network strategy, and thermal design envelope
• Architect and evaluate packaging technology choices, including silicon/glass interposers, EMIB/bridge, hybrid bonding, fan-out, and 3D stacking
• Lead co-design efforts across silicon design, floorplanning, PDN modeling, and mechanical/thermal reliability
• Work with stakeholders to define and validate advanced design rule roadmap for interposer, substrates and packages
• Work with vendors to define and validate equipment, process and material roadmap
• Explore technologies beyond what is currently available, make recommendations, and create and protect IP to maximize performance
• Explore technology feasibility and create proof-of-concept samples
• Collaborate with IP, Si design, package design, production and test teams
• Lead package material selection, substrate stack-up definition, mechanical modeling, and reliability analysis
• Partner with silicon design teams to co-optimize die floorplan, bump map, TSV, and RDL requirements
• Support HBM integration strategy (HBM2E / HBM3 / HBM3E) with interposer or bridge-based designs
• Work with OSATs / Foundry partners to evaluate process capability, manufacturability, yield, and cost
• Perform signal and power integrity trade-off analysis in partnership with SI/PI teams
• Drive package qualification and reliability validation to volume readiness

Senior Principal Engineer, Advanced Package Technology

• Develop packaging technology roadmap for AI XPU
• Explore technologies beyond what is currently available and make recommendations
• Create new package technology concepts and perform routing feasibility studies
• Define package architecture and lead co-design efforts across various engineering disciplines
• Partner with silicon design teams to co-optimize die floorplan and bump map requirements
• Drive package qualification and reliability validation to volume readiness

Principal Engineer, Advanced Package Technology

Program Manager

• Collaborate with global cross-functional teams including Foundry Engineering, Product and Test Engineering, Finance, Business Units, and Supply Chain
• Identify opportunities for improvement to sourcing methods and sourcing costs, product level yield improvement opportunities
• Drive a cross-functional effort to translate ideas into projects and changes to support corporate gross margin goals
• Lead/play an active role in driving a cross-functional task force to identify opportunities related to product and technology specific foundry and OSAT sourcing costs, product yields, benchmarking against best-in-class industry methods
• Drive a company-wide roadmap to implement changes both at the product level and to business processes with the right trade-offs to reduce cost and improve Gross Margins
• Identify and manage all aspects of the financial health of targeted semiconductor products from early ideation and design stages all the way through the end of life of the product
• Ensure that best practices for cost management are shared across different teams and changes are successfully implemented

Director – Supply Chain – Gross Margin Program Management

Marketing

• Define compelling products and solutions with clear value propositions that are validated and endorsed by leading target customers.
• Present product plans and generate excitement at all levels of organization from entry level engineer to CEO.
• Lead products and solutions business planning activities: market/technology trends, market sizing (TAM, SAM, SOM), key customers to win, competitive analysis, product positioning and pricing.
• Lead all product and solution requirement documents (MRD/PRD) activities to ensure engineering and cross-functional teams are all in-sync to execute what is needed to win key designs.
• Develop product and solution strategies with sales and cross-functional teams that yield design wins at targeted customer accounts.
• Drive entire product and solution life-cycle from cradle to grave.
• Develop multiple product family roadmaps for multiple market segments.
• Develop and drive sales funnel through team.
• Be held responsible for revenue generation as promised by product ROIs.
• Partner with sales to develop key customer account plans that cover key programs, supply chain partners, decision making tree, organization structure/contacts, and technology roadmap plans.
• Collaborate with engineering to develop reference design solutions for leading use cases and architecture engagements with leading customers and their platform partners.
• Sales & FAE training on market and product line plans.
• Help corporate marketing develop product line digital marketing and social media messaging.

Senior Director, Solutions Marketing

Supply Chain

• Collaborate with global cross-functional teams including Foundry Engineering, Product and Test Engineering, Finance, Business Units and Supply Chain
• Define sourcing methods, supplier selection, and negotiation plans towards meeting product ramp, capacity needs and cost targets
• Manage a team consisting of sourcing managers, commodity managers and buyers
• Drive cross-functional efforts to define sourcing methods and processes
• Lead cross-functional cost reviews to report actual versus target sourcing costs, risks and opportunities

Director – Supply Chain – Foundry, OSAT Procurement

• Responsible for high-performance hardware/system design of all-optical 400G/800G per lambda coherent DSP reference designs
• Architect, simulate and test the industry's best signal integrity with bandwidths exceeding 110GHz
• Collaborate with system, analog, digital, firmware, DFT, FA, validation, applications, etc. teams to define evaluation platform requirements
• Work with fellow hardware engineer(s) and firmware team for initial board bring-up
• Perform FA on boards and identify necessary repairs
• Develop and execute individual board validation plans and generate detailed validation reports
• Work with external PCB fabrication and assembly houses to ensure manufacturable designs and timely delivery of boards

Signal Integrity Engineer – HFSS, SiWave, PCB, Package - Senior Staff Engineer

Operations

• Direct day-to-day operations across Marvell’s global facility portfolio
• Oversee all hard FM and soft FM services ensuring reliability and operational consistency
• Lead 24/7/365 operational readiness, including emergency response protocols
• Manage strategic relationships with integrated facility management providers
• Own the global facilities operations budget and identify cost optimization initiatives
• Ensure compliance with applicable regulations and champion sustainability goals

Senior Director, Global Workplace Operations

Mechanical Engineer

• lead micro-architecture and RTL development and HW/SW co-design efforts
• define ASIC and/or block architecture, micro-architecture and register specification
• conduct detailed architectural and/or design requirement reviews with customers, cross-functional teams, IP Vendors
• implement a specification using RTL coding techniques and best practices
• work with the physical design teams, reviewing and providing guidance in floorplanning, power analysis, synthesis and timing signoff
• work with the Verification team on pre-silicon verification tasks such as reviewing the verification test plans, coverage analysis, full-chip simulation, performance analysis and debug
• help develop and/or evaluate design and verification methodologies and participate in improving existing ones
• provide mentorship to the more junior team members

Principal ASIC Design Engineer

Manager

• Define micro-architecture for complex blocks and subsystems
• Manage a team of 10–12 engineers
• Oversee the entire silicon lifecycle, including RTL design, synthesis, timing closure, and physical design coordination
• Partner with Verification, Physical Design (PD), and DFT (Design for Test) teams
• Align engineering roadmaps with business objectives and manage project budgets

Senior Staff Manager

• Work on verification of memory, AI/HPC or Die-2-Die subsystems of Marvell's AI/ML, Network processing, Compute, Memory Expander and Accelerated Compute SOCs and IPs
• Develop the architecture for a functional verification environment, including reference models and bus-functional monitors and drivers using System Verilog and UVM methodology
• Analyze designs and architectures to develop test strategies that will ensure functional correctness
• Develop verification testplan and write tests using random techniques and coverage analysis, and work with designers to ensure it is complete
• Debug failures and work with designers to resolve issues
• Contribute to the development and future direction of SoC verification methodologies and environments
• Provide leadership for a geographically dispersed team of verification professionals in pre-silicon validation of a highly complex SoC design