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Marvell Technology

Principal Design Verification Engineer

Marvell Technology

Principal Design Verification Engineer verifying cutting-edge semiconductor circuitry for AI/ML, network processing, and automotive solutions. Focus on developing verification environments using System Verilog and UVM methodology.

Posted 5/1/2026full-timeMorrisville • Massachusetts, North Carolina • 🇺🇸 United StatesLead💰 $160,400 - $237,320 per yearWebsite

Tech Stack

Tools & technologies
PerlPython

About the role

Key responsibilities & impact
  • Work on verification of Marvell's AI/ML, Network processing, Compute, Automotive, and Baseband SoCs and IPs
  • Develop the architecture for a functional verification environment, including reference models and bus-functional monitors and drivers using System Verilog and UVM methodology
  • Develop verification testplan and write tests using random techniques and coverage analysis
  • Work with designers to ensure the verification is complete
  • Develop tests and tune the environment to achieve coverage goals
  • Debug failures and work with designers to resolve issues
  • Architect, develop and maintain tools to streamline the design of state-of-the-art multicore SoCs
  • Experience with analysis/closure of code and functional coverage

Requirements

What you’ll need
  • Strong experience developing complex/random verification environments using System Verilog/UVM
  • Strong experience with writing and executing detailed verification test-plan
  • Strong experience with scripting languages such as Python or Perl and EDA verification tools
  • Strong experience with object-oriented design and implementation
  • Hands-on verification experience with subsystems such as ARM/processor, memory, networking, NoC, and Cache designs (preferred)
  • Experience with protocols such as AMBA, PCIe, Ethernet, I2C, SPI, and UART (preferred)
  • Working knowledge of C/C++ for modeling and code development (preferred)
  • Familiarity with Post-Silicon validation and debug (preferred)
  • Experience with Gate Level Simulations (preferred)
  • Excellent communication skills to interface internally and externally

Benefits

Comp & perks
  • Employee stock purchase plan with a 2-year look back
  • Family support programs to help balance work and home life
  • Robust mental health resources to prioritize emotional well-being
  • Recognition and service awards to celebrate contributions and milestones

ATS Keywords

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Hard Skills & Tools
System VerilogUVM methodologyverification test-planscripting languagesPythonPerlobject-oriented designGate Level Simulationsfunctional coveragerandom verification environments
Soft Skills
communication skills