K2 Space Corporation

Engineer

• Work with other engineering leads to develop and validate a novel high level vehicle architecture
• Develop novel algorithms for precise pointing of very large, flexible structures in earth orbit and beyond
• Develop novel slewing algorithms of very large, flexible structures in earth orbit and beyond
• Develop simulation and modeling tools to support vehicle and GNC trade studies. This includes mission design, controls analysis, and 6-DOF simulation development.
• Contribute to building the GNC organization by recruiting, hiring, and mentoring other engineers

Senior Navigation & Guidance Engineer

Hardware Engineer

• Contribute to the design and implementation of embedded firmware architecture, including boot flows, HAL components, drivers, and system services.
• Develop low‑level firmware in C/C++ (and assembly when required) for CPUs, DSPs, and microcontrollers within custom SoCs.
• Implement and maintain bootloaders, secure boot flows, and early hardware initialization sequences.
• Develop device drivers for on‑chip peripherals such as DMA engines, memory controllers, interconnects, SerDes, ADC/DAC interfaces, timers, and GPIO.
• Participate in pre‑silicon firmware development and validation activities.
• Support post‑silicon bring‑up, including power‑on sequencing, clock/reset initialization, memory bring‑up, and peripheral testing.
• Debug hardware/firmware interactions using JTAG, logic analyzers, oscilloscopes, trace tools, and custom debug instrumentation.
• Collaborate with SoC architects and designers to refine register maps, memory maps, interrupt structures, DMA flows, and debug infrastructure.
• Provide firmware input during design reviews and silicon development milestones.
• Bring up and integrate RTOS or bare‑metal environments.
• Support integration with higher‑level system software or application processors.
• Implement robust error handling, logging, and recovery mechanisms.
• Contribute to manufacturing test firmware, production firmware, and field diagnostics.
• Help ensure long‑term maintainability and scalability of firmware across multiple SoC generations.

Senior Embedded Firmware Engineer

Mechanical Engineer

• Define ASIC package architecture for FC-BGA and MCM solutions, including substrate stack-up, ball-map strategy, power delivery, signal breakout, and mechanical constraints.
• Lead package-level trade studies across cost, performance, power integrity (PI), signal integrity (SI), thermal, manufacturability, and reliability.
• Establish package design standards, methodologies, and best practices.
• Drive detailed design of FC-BGA packages for high-pin-count ASICs with high-speed SerDes, dense power grids, and RF signal content.
• Define and review substrate stack-ups, via strategies, impedance control, escape routing, and reference plane planning.
• Partner with silicon, RF, and systems teams to co-optimize die floorplans and package interfaces.
• Support package-level SI/PI strategy, including high-speed digital interfaces, power delivery network (PDN) design, and decoupling strategy
• Lead thermal architecture at the package level, including lid selection, TIMs, heat-spreaders, and mechanical interfaces to system cooling.
• Drive material selection, substrate technology choices, and assembly process optimization.

Senior ASIC Package Design Engineer

• Own ASIC package architecture for FC-BGA and MCM solutions, including substrate stack-up, ball-map strategy, power delivery, signal breakout, and mechanical constraints.
• Lead package-level trade studies across cost, performance, power integrity (PI), signal integrity (SI), thermal, manufacturability, and reliability.
• Define long-term packaging roadmap aligned with future ASIC nodes, bandwidth scaling, and multi-die integration.
• Establish organizational package design standards, methodologies, and best practices.
• Drive detailed design of FC-BGA packages for high-pin-count ASICs with high-speed SerDes, dense power grids, and RF signal content.
• Define and review substrate stack-ups, via strategies, impedance control, escape routing, and reference plane planning.
• Partner with silicon, RF, and systems teams to co-optimize die floorplans and package interfaces.
• Own package-level SI/PI strategy, including high-speed digital interfaces (e.g., SerDes, JESD, Interlaken), power delivery network (PDN) design, and decoupling strategy
• Lead thermal architecture at the package level, including lid selection, TIMs, heat-spreaders, and mechanical interfaces to system cooling.
• Serve as the primary technical interface to substrate vendors, assembly houses, and OSATs.
• Drive material selection, substrate technology choices, and assembly process optimization.

Principal ASIC Package Design Engineer

• Execute the complete physical design flow for complex SoC blocks and/or top-level integration, including synthesis, floorplanning, place & route, CTS, STA, and physical verification.
• Perform timing closure and optimization across multiple corners and modes using industry-standard tools.
• Collaborate with DFT teams to ensure clean timing convergence.
• Develop and maintain scripts and automation to improve flow efficiency and consistency.
• Support physical sign-off activities including DRC/LVS, STA, EM, Signal Integrity and power analysis.
• Assist in chip-level integration, timing and functional ECOs, and tapeout preparation.
• Contribute to methodology development, tool evaluation, and flow documentation.

ASIC Physical Design Engineer

• Work on the RTL-to-Synthesis flow: Do synthesis at block and top level, Work with physical design team to integrate the floorplan information for physical synthesis.
• Develop and maintain design methodologies, scripts, and automation to optimize performance, power, and area (PPA).
• Collaborate with front-end engineers to assure timing closure, and efficient design iteration.
• Drive timing closure across multiple voltage and process corners, including sign-off with foundry-qualified tools.
• Own Lint, CDC and UPF checks and drive collaboration to close out issues.
• Develop an end to end formal verification methodology without any gap to deliver on full confidence functionality between the RTL and the post layout netlist.
• Manage and technically guide external physical design partners and service vendors, ensuring alignment on milestones, deliverables, and quality standards.
• Work with EDA vendors to debug and optimize tool flows, and evaluate new methodologies.
• Support chip bring-up and debug through close collaboration with post-silicon and test teams.
• Support your product through production and spaceflight.

ASIC Synthesis and Timing Engineer

• Own the complete RTL-to-Synthesis flow: Do synthesis at block and top level
• Work with physical design team to integrate the floorplanning information for physical synthesis
• Develop and maintain design methodologies, scripts, and automation to optimize performance, power, and area (PPA)
• Collaborate with front-end and verification teams to ensure clean handoffs, timing closure, and efficient design iteration
• Drive timing closure across multiple voltage and process corners, including sign-off with foundry-qualified tools
• Own Lint, CDC and UPF checks and drive collaboration to close out issues
• Develop an end to end formal verification methodology without any gap to deliver on full confidence functionality between the RTL and the post layout netlist
• Manage and technically guide external physical design partners and service vendors, ensuring alignment on milestones, deliverables, and quality standards
• Work with EDA vendors to debug and optimize tool flows, and evaluate new methodologies
• Support chip bring-up and debug through close collaboration with post-silicon and test teams
• Support your product through production and spaceflight.