K2 Space Corporation

Mechanical Engineer

• Verify the functionality, performance, and robustness of custom silicon designs.
• Define verification approach and contribute to methodology.
• Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.
• Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.
• Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate.
• Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios.
• Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues.
• Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off.
• Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations.
• Participate in design reviews, microarchitecture discussions, and influence design-for-verification (DFV) best practices.
• Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers to ensure end-to-end coverage and test.
• Support silicon bring-up and post-silicon validation through test reuse, diagnostics, and debug analysis.
• Participate in ASIC team interviews.
• Drive advancement of DV methodologies and improvements.
• Manage external IP providers and verification partners when needed.
• Take lead on large and/or complex systems.

Principal ASIC Design Verification Engineer

Engineer

• Develop high-level behavioral models for analog and mixed-signal IP (ADCs, DACs, PLLs, LDOs, RF front-end blocks, biasing, amplifiers, etc.)
• Create abstracted models using Verilog, Verilog-AMS, or SystemVerilog
• Develop regression infrastructure and mixed-signal testbenches enabling co-simulation (digital + analog)
• Integrate AMS models into digital verification environments (UVM-based)
• Define and build the mixed-signal verification methodology for top-level SoC and subsystem verification
• Support architectural exploration through early-phase modeling and system-level simulations
• Collaborate with analog/RF designers to capture real-world analog behaviors and map them into accurate behavioral abstractions
• Work with digital and verification teams to ensure seamless integration of AMS models
• Provide modeling and verification insights during architectural reviews, PDR/CDR, and silicon bring-up
• Act as technical leader and subject-matter expert.

Senior Mixed-Signal Verification Engineer

• Define and implement DFT architecture for mixed-signal SoCs, including scan, MBIST, LBIST, and boundary scan.
• Lead RTL-level DFT insertion, scan chain insertion and optimization, test point insertion, and low-power DFT methodologies.
• Own ATPG flow development and execution by generating high-quality stuck-at, transition, and path delay test patterns. Drive coverage closure and pattern optimization and debug pattern failure and silicon correlation.
• Develop and integrate DFT strategies for mixed-signal blocks, including wrapper-based approaches, and analog test interfaces and BIST solutions.
• Collaborate with RTL, DV, and PD teams to ensure clean DFT integration at RTL and gate-level, and timing and physical constraints alignment (scan reordering, compression, etc.).
• Drive DFT verification and signoff, including Scan/ATPG coverage metrics, DRC/Lint checks (DFT rule compliance), gate-level simulation and pattern validation.
• Support bring-up and silicon debug activities by analyzing tester failures, yield issues, and ATPG pattern correlation with silicon behavior.
• Contribute to methodology development, automation, and flow improvements.

Senior DFT Engineer

Designer

• Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.
• Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.
• Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate.
• Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios.
• Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues.
• Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off.
• Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations.
• Participate in design reviews, microarchitecture discussions, and influence design-for-verification (DFV) best practices.
• Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers to ensure end-to-end coverage and test.
• Support silicon bring-up and post-silicon validation through test reuse, diagnostics, and debug analysis.
• Participate in ASIC team interviews.
• Contribute to advancement of DV methodologies and improvements.
• Engage external IP providers and verification partners when needed.

Senior ASIC Design Verification Engineer

• Develop high-level behavioral models for analog and mixed-signal IP (ADCs, DACs, PLLs, LDOs, RF front-end blocks, biasing, amplifiers, etc.).
• Create abstracted models using Verilog, Verilog-AMS, or SystemVerilog.
• Develop regression infrastructure and mixed-signal testbenches enabling co-simulation (digital + analog).
• Integrate AMS models into digital verification environments (UVM-based).
• Define and build the mixed-signal verification methodology for top-level SoC and subsystem verification.
• Support architectural exploration through early-phase modeling and system-level simulations.
• Collaborate with analog/RF designers to capture real-world analog behaviors and map them into accurate behavioral abstractions.
• Work with digital and verification teams to ensure seamless integration of AMS models.
• Provide modeling and verification insights during architectural reviews, PDR/CDR, and silicon bring-up.
• Act as technical leader and subject-matter expert.

Mixed-Signal Behavioral Modeling Engineer

• Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.
• Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.
• Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate.
• Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios.
• Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues.
• Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off.
• Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations.
• Participate in design reviews and microarchitecture discussions.