K2 Space Corporation

Mechanical Engineer

• Design, implement, and verify digital blocks for wireless SoCs using SystemVerilog or Verilog
• Translate algorithmic and architectural specifications into synthesizable RTL
• Implement DSP functions such as filtering, FFT/IFFT, or beamforming
• Convert chip specifications into RTL using internal IPs and external IPs
• Design and develop RTL for interfaces, power management, clocking, reset, test & debug
• Partner with analog/mixed-signal teams to define digital-analog interfaces, calibration engines, and control logic
• Optimize designs for power, performance, and area (PPA) and support timing closure through synthesis and backend collaboration
• Contribute to block-level integration, synthesis, and timing closure
• Participate in design reviews, functional verification, and timing closure
• Participate in chip bring-up and lab validation of complex digital subsystems
• Support your product through production and spaceflight

Senior Digital ASIC Design Engineer

• Lead the design and development of high-performance, high-speed ADC and DAC architectures.
• Lead the architecture definition and implementation of low-jitter, low-power integer-N and fractional-N PLLs, frequency synthesizers and clocking systems.
• Own the planning and execution of simulations for critical mixed-signal sub-systems at the transceiver level to ensure system performance and compliance.
• Own the package design strategy, modeling, and cross-functional integration.
• Lead cross-functional efforts to integrate circuits advanced FinFET-based SoCs, ensuring layout, parasitic, and floor planning alignment.
• Drive full lifecycle design including specification, modeling (Verilog-A/AMS), schematic design, simulation, post-layout verification, and silicon validation.
• Perform design optimization for power, area, and performance in advanced FinFET nodes.
• Develop and maintain design documentation and support post-silicon bring-up and characterization.
• Support your product through production and spaceflight.
• Act as technical leader and subject-matter expert helping to teach, grow, and mentor others in the team.

Principal Mixed-Signal IC Design Engineer

• Own the architecture, microarchitecture, RTL implementation, and integration of key digital blocks in wireless SoCs.
• Collaborate with system architects to translate high-level DSP algorithms into efficient hardware implementations.
• Drive end-to-end development of DSP systems (e.g., filters, beamformers, FFT/IFFT engines).
• Convert chip specifications into RTL using internal IPs and external IPs.
• Design and develop RTL for interfaces, power management, clocking, reset, test & debug.
• Partner with analog/mixed-signal teams to define digital-analog interfaces, calibration engines, and control logic.
• Optimize designs for power, performance, and area (PPA) and support timing closure through synthesis and backend collaboration.
• Lead or contribute to verification planning and validation of complex digital subsystems.
• Participate in chip bring-up and lab validation of complex digital subsystems.
• Support your product through production and spaceflight.
• Act as a technical leader and subject-matter expert, helping to teach, grow, and mentor others in the team.

Principal Digital ASIC Design Engineer

• Design, implement, and verify digital blocks for wireless SoCs using SystemVerilog or Verilog.
• Translate algorithmic and architectural specifications into synthesizable RTL.
• Implement DSP functions such as filtering, FFT/IFFT, or beamforming.
• Convert chip specifications into RTL using internal IPs and external IPs.
• Design and develop RTL for interfaces, power management, clocking, reset, test & debug.
• Partner with analog/mixed-signal teams to define digital-analog interfaces, calibration engines, and control logic.
• Optimize designs for power, performance, and area (PPA) and support timing closure through synthesis and backend collaboration.
• Contribute to block-level integration, synthesis, and timing closure.
• Participate in design reviews, functional verification, and timing closure.
• Participate in chip bring-up and lab validation of complex digital subsystems.
• Support your product through production and spaceflight.

Digital ASIC Design Engineer

• Lead and manage a team of digital design engineers
• Contribute to design and implementation of microarchitecture and RTL
• Collaborate with system architects to translate high-level algorithms
• Optimize designs for power, performance, and area
• Mentor junior engineers and contribute to team technical growth

Lead Digital ASIC Design Engineer

• Design and develop high-performance, high-speed ADC and DAC architectures.
• Architect and implement low-jitter, low-power integer-N and fractional-N PLLs, frequency synthesizers and clocking systems.
• Engage with cross-functional analog, digital, DV, firmware, SoC architecture, technology, packaging, silicon validation, production test, and manufacturing teams to implement circuits and sub-systems.
• Drive full lifecycle design including specification, modeling (Verilog-A/AMS), schematic design, simulation, post-layout verification, and silicon validation.
• Perform design optimization for power, area, and performance in advanced FinFET nodes.
• Develop and maintain design documentation and support post-silicon bring-up and characterization.
• Support your product through production and spaceflight.
• Act as technical leader and subject-matter expert helping to teach, grow, and mentor others in the team.

Senior Mixed-Signal IC Design Engineer

Engineer

• Work with other engineering leads to set the direction and develop novel vehicle architecture
• Develop novel algorithms for precise pointing of very large, flexible structures in earth orbit and beyond
• Develop novel slewing algorithms of very large, flexible structures in earth orbit and beyond
• Develop simulation and modeling tools to support vehicle and GNC trade studies. This includes mission design, controls analysis, and 6-DOF simulation development.
• Integral to building the GNC organization by recruiting, hiring, and mentoring other engineers