K2 Space Corporation

Mechanical Engineer

• Execute the complete physical design flow for complex SoC blocks and top-level integration, including synthesis, floorplanning, place & route, CTS, STA, and physical verification.
• Perform timing closure and optimization across multiple corners and modes using industry-standard tools.
• Collaborate with front-end, verification, and DFT teams to ensure clean handoff and predictable convergence.
• Work with external physical design service providers and internal leads to review deliverables, resolve issues, and ensure schedule alignment.
• Develop and maintain scripts and automation to improve flow efficiency and consistency.
• Support physical sign-off activities including DRC/LVS, IR drop, EM, and power analysis.
• Assist in chip-level integration, ECOs, and tapeout preparation.
• Contribute to methodology development, tool evaluation, and flow documentation.
• Support your product through production and spaceflight.

Senior ASIC Physical Design Engineer

• Own the complete RTL-to-GDSII flow: synthesis, floorplanning, place & route, clock tree synthesis (CTS), static timing analysis (STA), physical verification (DRC/LVS), and sign-off.
• Develop and maintain physical design methodologies, scripts, and automation to optimize performance, power, and area (PPA).
• Collaborate with front-end and verification teams to ensure clean handoffs, timing closure, and efficient design iteration.
• Drive timing closure across multiple voltage and process corners, including sign-off with foundry-qualified tools.
• Partner with package, SI/PI, and test teams for package-aware floorplanning and chip-to-board integration.
• Manage and technically guide external physical design partners and service vendors, ensuring alignment on milestones, deliverables, and quality standards.
• Work with EDA vendors to debug and optimize tool flows, and evaluate new methodologies.
• Support chip bring-up and debug through close collaboration with post-silicon and test teams.
• Support your product through production and spaceflight.

Principal ASIC Physical Design Engineer

Designer

• Execute high-quality layout for RF, analog, and mixed-signal blocks.
• Contribute to top-level layout integration.
• Contribute to layout strategies to meet performance targets.
• Ensure robust implementation of matching and symmetry.
• Collaborate with RF/analog designers and digital implementation teams.
• Participate in establishing layout review processes.
• Drive full-chip physical signoff.
• Own tapeout readiness and interface with foundry and EDA partners.

Senior RFIC Layout Designer

Engineer

• Develop high-level behavioral models for analog and mixed-signal IP (ADCs, DACs, PLLs, LDOs, RF front-end blocks, biasing, amplifiers, etc.)
• Create abstracted models using Verilog, Verilog-AMS, or SystemVerilog.
• Develop regression infrastructure and mixed-signal testbenches enabling co-simulation (digital + analog).
• Integrate AMS models into digital verification environments (UVM-based).
• Define and build the mixed-signal verification methodology for top-level SoC and subsystem verification.
• Support architectural exploration through early-phase modeling and system-level simulations.
• Collaborate with analog/RF designers to capture real-world analog behaviors and map them into accurate behavioral abstractions.
• Work with digital and verification teams to ensure seamless integration of AMS models.
• Provide modeling and verification insights during architectural reviews, PDR/CDR, and silicon bring-up.
• Act as technical leader and subject-matter expert.

Senior Mixed-Signal Behavioral Modeling Engineer

• As a Principal GNC engineer, be a core driver of spacecraft GNC architecture
• Execute detailed trade studies on spacecraft’s guidance, attitude control, and orbit estimation systems
• Anticipate company needs and set up infrastructure for core and future business
• Own and execute the Verification and Validation plan for the GNC stack in first 3 months
• Support launch and on-orbit operations of K2 spacecraft bus – the Mega in first 6 months
• Own planning and development of future tooling to support GNC for future missions in first year

Principal Guidance, Navigation, Control Engineer

Hardware Engineer

• Define the overall embedded firmware architecture for custom SoCs, including boot flows, hardware abstraction layers (HALs), drivers, and system services.
• Develop low-level firmware in C/C++ (and assembly where needed) for CPUs, DSPs, and microcontrollers embedded within SoCs.
• Own boot ROM, first-stage bootloader, secure boot, and early initialization sequences.
• Design and implement device drivers for on-chip peripherals (DMA, memory controllers, interconnects, SerDes, ADC/DAC interfaces, timers, GPIO, etc.).
• Lead pre-silicon firmware development.
• Drive post-silicon bring-up, including power-on sequencing, clocking, reset, memory bring-up, and peripheral validation.
• Debug complex HW/FW issues using JTAG, logic analyzers, oscilloscopes, trace tools, and custom debug hooks.
• Collaborate with SoC architects to define register maps, memory maps, interrupts, DMA flows, and debug infrastructure.
• Provide firmware input during architecture, PDR/CDR, and silicon reviews.
• Bring up and integrate RTOS or bare-metal.
• Support integration with higher-level system software or application processors as needed.
• Implement robust error handling, logging, and recovery mechanisms.
• Support manufacturing test, production firmware, and field diagnostics.
• Contribute to long-term firmware maintainability and scalability across multiple SoC generations.

Principal Embedded Firmware Engineer

• Design, implement, and verify digital blocks for wireless SoCs using SystemVerilog or Verilog
• Translate algorithmic and architectural specifications into synthesizable RTL
• Implement DSP functions such as filtering, FFT/IFFT, or beamforming
• Convert chip specifications into RTL using internal IPs and external IPs
• Design and develop RTL for interfaces, power management, clocking, reset, test & debug
• Partner with analog/mixed-signal teams to define digital-analog interfaces, calibration engines, and control logic
• Optimize designs for power, performance, and area (PPA) and support timing closure through synthesis and backend collaboration
• Contribute to block-level integration, synthesis, and timing closure
• Participate in design reviews, functional verification, and timing closure
• Participate in chip bring-up and lab validation of complex digital subsystems
• Support your product through production and spaceflight

Senior Digital ASIC Design Engineer

• Lead the design and development of high-performance, high-speed ADC and DAC architectures.
• Lead the architecture definition and implementation of low-jitter, low-power integer-N and fractional-N PLLs, frequency synthesizers and clocking systems.
• Own the planning and execution of simulations for critical mixed-signal sub-systems at the transceiver level to ensure system performance and compliance.
• Own the package design strategy, modeling, and cross-functional integration.
• Lead cross-functional efforts to integrate circuits advanced FinFET-based SoCs, ensuring layout, parasitic, and floor planning alignment.
• Drive full lifecycle design including specification, modeling (Verilog-A/AMS), schematic design, simulation, post-layout verification, and silicon validation.
• Perform design optimization for power, area, and performance in advanced FinFET nodes.
• Develop and maintain design documentation and support post-silicon bring-up and characterization.
• Support your product through production and spaceflight.
• Act as technical leader and subject-matter expert helping to teach, grow, and mentor others in the team.

Principal Mixed-Signal IC Design Engineer

• Own the architecture, microarchitecture, RTL implementation, and integration of key digital blocks in wireless SoCs.
• Collaborate with system architects to translate high-level DSP algorithms into efficient hardware implementations.
• Drive end-to-end development of DSP systems (e.g., filters, beamformers, FFT/IFFT engines).
• Convert chip specifications into RTL using internal IPs and external IPs.
• Design and develop RTL for interfaces, power management, clocking, reset, test & debug.
• Partner with analog/mixed-signal teams to define digital-analog interfaces, calibration engines, and control logic.
• Optimize designs for power, performance, and area (PPA) and support timing closure through synthesis and backend collaboration.
• Lead or contribute to verification planning and validation of complex digital subsystems.
• Participate in chip bring-up and lab validation of complex digital subsystems.
• Support your product through production and spaceflight.
• Act as a technical leader and subject-matter expert, helping to teach, grow, and mentor others in the team.

Principal Digital ASIC Design Engineer

• Design, implement, and verify digital blocks for wireless SoCs using SystemVerilog or Verilog.
• Translate algorithmic and architectural specifications into synthesizable RTL.
• Implement DSP functions such as filtering, FFT/IFFT, or beamforming.
• Convert chip specifications into RTL using internal IPs and external IPs.
• Design and develop RTL for interfaces, power management, clocking, reset, test & debug.
• Partner with analog/mixed-signal teams to define digital-analog interfaces, calibration engines, and control logic.
• Optimize designs for power, performance, and area (PPA) and support timing closure through synthesis and backend collaboration.
• Contribute to block-level integration, synthesis, and timing closure.
• Participate in design reviews, functional verification, and timing closure.
• Participate in chip bring-up and lab validation of complex digital subsystems.
• Support your product through production and spaceflight.

Digital ASIC Design Engineer

• Lead and manage a team of digital design engineers
• Contribute to design and implementation of microarchitecture and RTL
• Collaborate with system architects to translate high-level algorithms
• Optimize designs for power, performance, and area
• Mentor junior engineers and contribute to team technical growth

Lead Digital ASIC Design Engineer

• Design and develop high-performance, high-speed ADC and DAC architectures.
• Architect and implement low-jitter, low-power integer-N and fractional-N PLLs, frequency synthesizers and clocking systems.
• Engage with cross-functional analog, digital, DV, firmware, SoC architecture, technology, packaging, silicon validation, production test, and manufacturing teams to implement circuits and sub-systems.
• Drive full lifecycle design including specification, modeling (Verilog-A/AMS), schematic design, simulation, post-layout verification, and silicon validation.
• Perform design optimization for power, area, and performance in advanced FinFET nodes.
• Develop and maintain design documentation and support post-silicon bring-up and characterization.
• Support your product through production and spaceflight.
• Act as technical leader and subject-matter expert helping to teach, grow, and mentor others in the team.