ASIC Design Verification Engineer

K2 Space Corporation

ASIC Design Verification Engineer verifying functionality, performance, and robustness of custom silicon designs for K2 Space startup. Involves shaping first-generation silicon with high ownership and technical engagement.

Posted 6/24/2026full-timeRemote • 🇺🇸 United StatesMid-LevelSenior💰 $130,000 - $200,000 per yearWebsite

Tech Stack

Tools & technologies

PerlPython

About the role

Key responsibilities & impact

Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.
Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.
Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate.
Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios.
Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues.
Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off.
Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations.
Participate in design reviews and microarchitecture discussions.

Requirements

What you’ll need

B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
3+ years of experience in ASIC/SoC verification.
Solid understanding of SystemVerilog, digital logic, and hardware verification flows.
Proficiency with a simulation (VCS, Xcelium, Questa), waveform debug (Verdi, SimVision) and coverage tool.
Experience with test planning, testbench development, constrained-random testing, and coverage analysis.
Familiarity with a scripting language (ex: Python, Perl, TCL) and revision control system (ex: Git).

Benefits

Comp & perks

Comprehensive benefits package including paid time off
medical/dental/vision coverage
life insurance
paid parental leave
many other perks

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills & Tools

SystemVerilogUVMSystemVerilog Assertionsconstrained-random testingdirected testingfunctional coveragecode coverageassertion coveragetest planningtestbench development

Soft Skills

collaborationroot-cause analysisproblem-solvingcommunication