Senior ASIC Design Verification Engineer

K2 Space Corporation

Senior ASIC Design Verification Engineer verifying functionality and performance of custom silicon designs at K2 Space. Collaborating with multiple engineering teams to shape first-generation silicon.

Posted 6/24/2026full-timeRemote • 🇺🇸 United StatesSenior💰 $170,000 - $250,000 per yearWebsite

Tech Stack

Tools & technologies

PerlPython

About the role

Key responsibilities & impact

Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.
Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.
Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate.
Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios.
Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues.
Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off.
Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations.
Participate in design reviews, microarchitecture discussions, and influence design-for-verification (DFV) best practices.
Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers to ensure end-to-end coverage and test.
Support silicon bring-up and post-silicon validation through test reuse, diagnostics, and debug analysis.
Participate in ASIC team interviews.
Contribute to advancement of DV methodologies and improvements.
Engage external IP providers and verification partners when needed.

Requirements

What you’ll need

B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
5+ years of experience in ASIC/SoC verification.
Solid understanding of SystemVerilog, digital logic, RTL design, and hardware verification flows.
Proficiency with a simulation (VCS, Xcelium, Questa), waveform debug (Verdi, SimVision), coverage tool, and scripting languages (ex: Python, Perl, TCL).
Experience with test planning, UVM-based testbench development, constrained-random testing, functional coverage, and SystemVerilog assertions.
Experience with regression management, coverage analysis, revision control (Git), and CI/CD automation.
Understanding of several industry-standard interfaces (ex: APB/AHB/AXI).
Familiarity with embedded processor-based designs and firmware/bare metal coding (ex: C, C++).

Benefits

Comp & perks

Comprehensive benefits package including paid time off
Medical/dental/vision coverage
Life insurance
Paid parental leave
Equity in the company

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills & Tools

SystemVerilogUVMAssertionsconstrained-random testingfunctional coveragedigital logicRTL designtest planningscripting languagesdebug analysis

Soft Skills

collaborationroot-cause analysisinfluencecommunicationproblem-solving