Senior DFT Engineer

K2 Space Corporation

Senior Design-for-Test Engineer at K2 Space developing DFT architecture and ensuring silicon success. Collaborating with design, verification, and physical design teams to optimize test coverage.

Posted 6/24/2026full-timeRemote • 🇺🇸 United StatesSenior💰 $170,000 - $250,000 per yearWebsite

ATS Keywords

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Hard Skills

DFT architectureRTL-level DFT insertionATPG flow developmentscan chain insertionlow-power DFT methodologiestest point insertioncoverage analysispattern optimizationsilicon correlationmixed-signal integration

Soft Skills

collaborationdebuggingmethodology developmentautomationflow improvements

Tools & Technologies

ATPG toolsgate-level simulationDFT rule complianceDRC checksLint checks

Certifications & Qualifications

B.S. in Electrical EngineeringM.S. in Electrical Engineering

Industry Keywords

mixed-signal SoCsscanMBISTLBISTfault modelscompression techniquescoverage closureanalog test interfacesBIST solutionstiming constraints

About the role

Key responsibilities & impact

Define and implement DFT architecture for mixed-signal SoCs, including scan, MBIST, LBIST, and boundary scan.
Lead RTL-level DFT insertion, scan chain insertion and optimization, test point insertion, and low-power DFT methodologies.
Own ATPG flow development and execution by generating high-quality stuck-at, transition, and path delay test patterns. Drive coverage closure and pattern optimization and debug pattern failure and silicon correlation.
Develop and integrate DFT strategies for mixed-signal blocks, including wrapper-based approaches, and analog test interfaces and BIST solutions.
Collaborate with RTL, DV, and PD teams to ensure clean DFT integration at RTL and gate-level, and timing and physical constraints alignment (scan reordering, compression, etc.).
Drive DFT verification and signoff, including Scan/ATPG coverage metrics, DRC/Lint checks (DFT rule compliance), gate-level simulation and pattern validation.
Support bring-up and silicon debug activities by analyzing tester failures, yield issues, and ATPG pattern correlation with silicon behavior.
Contribute to methodology development, automation, and flow improvements.

Requirements

What you’ll need

B.S. or M.S. in Electrical Engineering or related field.
7+ years of experience in DFT for complex SoCs.
Strong hands-on experience with RTL DFT insertion (scan, compression, test points) and ATPG tools and flows.
Deep understanding of scan architectures, compression techniques, fault models (stuck-at, transition, bridging, path delay), coverage analysis and closure strategies.
Experience with low-power DFT techniques.
Familiarity with mixed-signal integration challenges and test methodologies.
Strong debugging skills across RTL, gate-level, and silicon.

Benefits

Comp & perks

Comprehensive benefits package including paid time off
Medical/dental/vision coverage
Life insurance
Paid parental leave
Many other perks