Principal ASIC Design Verification Engineer

K2 Space Corporation

Principal ASIC Design Verification Engineer verifying silicon designs for K2 Space's satellite technology. Leading verification strategies in a fast-paced, innovative space startup environment.

Posted 6/26/2026full-timeRemote • 🇺🇸 United StatesLead💰 $190,000 - $285,000 per yearWebsite

Tech Stack

Tools & technologies

PerlPython

About the role

Key responsibilities & impact

Verify the functionality, performance, and robustness of custom silicon designs.
Define verification approach and contribute to methodology.
Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.
Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.
Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate.
Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios.
Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues.
Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off.
Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations.
Participate in design reviews, microarchitecture discussions, and influence design-for-verification (DFV) best practices.
Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers to ensure end-to-end coverage and test.
Support silicon bring-up and post-silicon validation through test reuse, diagnostics, and debug analysis.
Participate in ASIC team interviews.
Drive advancement of DV methodologies and improvements.
Manage external IP providers and verification partners when needed.
Take lead on large and/or complex systems.

Requirements

What you’ll need

B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
10+ years of experience in ASIC/SoC verification.
Solid understanding of SystemVerilog, digital logic, RTL design, DFT, and hardware design and verification flows.
Proficiency with several simulation (VCS, Xcelium, Questa), waveform debug (Verdi, SimVision), coverage tools, and scripting languages (ex: Python, Perl, TCL).
Experience with test planning, UVM-based testbench development, constrained-random testing, functional coverage, and SystemVerilog assertions.
Experience with regression management, coverage analysis, revision control (ex: Git), CI/CD automation, and gate-level simulation.
Experience with developing and integrating reference models.
Experience with embedded processor-based designs and firmware/bare metal coding (ex: C, C++).
Understanding of many industry-standard interfaces (ex: APB/AHB/AXI).
Involvement in post-silicon validation planning and execution.

Benefits

Comp & perks

Comprehensive benefits package including paid time off
Medical/dental/vision coverage
Life insurance
Paid parental leave
Other perks

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills & Tools

SystemVerilogUVMdigital logicRTL designDFTfunctional coverageSystemVerilog Assertionsconstrained-random testingtest planningembedded processor-based designs

Soft Skills

collaborationleadershipproblem-solvingcommunicationroot-cause analysisinfluenceadvancement of methodologiesmanagement