Cornelis Networks

Engineer

• Own and evolve the tools, flows, automation, and AI capabilities underpinning the entire DV lifecycle—from UVM testbench bring-up and coverage analytics to large-scale regressions, CI/CD, intelligent triage, and release pipelines
• Collaborate across full-stack software, hardware, RTL design, emulation, and post-silicon teams to deliver robust, reproducible, and data-driven DV at scale
• Architect, implement, and maintain DV automation and regression infrastructure
• Build scalable, reliable pipelines for multi-simulator (e.g., VCS, Xcelium, Questa) compilation, elaboration, and execution
• Own coverage collection/merge (UCIS), results triage, flake detection, and auto-bisection workflows
• Implement resource- and license-aware scheduling; optimize throughput and cost
• Own, maintain, and report simulation performance metrics across regression, debug, and coverage workflows
• Apply AI/ML to accelerate DV flows, debug, and triage
• Build high-quality datasets from logs, coverage (UCIS), waves, bug trackers, and metadata; define labeling and data hygiene standards
• Develop models and heuristics for failure clustering, deduplication, auto-classification, and bug-assignment suggestions
• Implement anomaly detection for regressions (e.g., pass-rate drops, performance regressions, license/queue anomalies)
• Prioritize and select tests/seeds using coverage- and history-informed ranking; predictively gate changes pre-merge
• Integrate LLMs for log/wave summarization, root-cause hints, and knowledge-base retrieval; surface insights via PR comments, dashboards, or chat interfaces
• Enforce reproducibility and governance for datasets, features, and prompts
• Develop CI/CD and release pipelines for DV
• Create dynamic pre-merge checks, nightly/weekly gating, and sign-off flows using GitHub Actions and/or Jenkins
• Track artifacts (binaries, waves, logs), tool/seed manifests, and ensure reproducibility for audits and tapeout
• Define policies for wave capture, retention, and on-demand replay
• Build high-quality tooling and libraries
• Author robust Python/Tcl/Bash utilities, CLI tools, and templates for common DV tasks
• Standardize environment setup (containers/Modules), tool configs, and runbooks
• Integrate lint/CDC/formal flows and quality gates into automated pipelines
• Operate at scale on compute infrastructure
• Integrate with job schedulers (e.g., SLURM/LSF/PBS/SGE) and coordinate with IT/SRE on storage, networking, and license servers
• Containerize EDA environments (Docker/Podman/Singularity) for consistency and portability
• Partner with DV and design engineers
• Support ground-up UVM environment development at block/unit/SoC levels with an emphasis on reusability and instrumentation
• Enable functional/code coverage closure through standardized testbench hooks and metrics
• Improve debuggability via log structuring, automated triage, and viewer integrations (e.g., Verdi/DVE)
• Drive observability and continuous improvement
• Publish dashboards for pass rate, coverage, performance, and queue/license health (e.g., Grafana/ELK/Prometheus)
• Document flows, teach best practices, and mentor peers on Git/GitHub, automation, and AI-assisted workflows

ASIC Verification Engineer – Automation

Full-stack Engineer

• Lead the design of robust, scalable solutions for integrating Cornelis Networks' platform and fabric management software with Kubernetes
• Build and maintain custom Kubernetes Operators and Controllers in Go to manage the lifecycle of our software and hardware components within a cluster
• Develop solutions that allow for the seamless orchestration of our high-performance fabric services and platform management tools alongside other containerized workloads
• Work on extending Kubernetes for managing specialized hardware, scheduling, and networking requirements unique to HPC and AI workloads
• Partner with the core platform, fabric, and hardware teams to ensure a cohesive and performant end-to-end solution
• Engage with the open-source community and contribute to relevant projects within the cloud-native ecosystem
• Author high-quality technical documentation and champion best practices for software development in a cloud-native environment

Senior Software Engineer, Kubernetes Platform, Fabric Integration

Business Development Rep

• Hunt for new opportunities across Enterprises and Co-Location data center providers by proactively identifying, engaging, and developing relationships with key influencers within each organization
• Open doors at target accounts and establish Cornelis as a trusted partner by leveraging persistence, creativity, and strong customer engagement
• Align technology roadmaps between Cornelis and cloud-native customers to influence infrastructure decisions in AI and enterprise cloud deployments
• Works in tandem with the Enterprise Account Executives to drive the AI opportunities at their respective accounts, creating demand for Cornelis Networks products outside of HPC environments
• Represent Cornelis Networks at Enterprise and Cloud AI events, trade shows, executive forums, and industry conferences
• Serve as the customer advocate internally, providing structured feedback to shape Cornelis’ product and market strategies
• Operate with grit and resilience, navigating complex, matrixed partner organizations to build alignment from field sellers to executive decision-makers.

Senior Business Development Manager – Enterprise, Co-Lo AI

• Develop optimized C code for embedded processors
• Collaborate with architects and hardware engineers to co-design next-generation hardware given software requirements
• Evaluate system architecture and make recommendations as required
• Develop and implement standard processes for unit test, collaborate on CI/CD implementations
• Review other team members’ design documents and pull requests
• Layout and establish design documents with the engineering team
• Review and provide strong feedback on firmware and software architecture specifications and design specifications
• Work with the Software Engineering Manager to identify tasks and build out schedules

Senior Software Engineer

Mechanical Engineer

• Implementation of the advanced ethernet protocols for the next generation ethernet ASICs.
• Write micro architecture specifications.
• Pre-silicon: Define timing constraints for the RTL block and work with Physical Design engineers for timing optimization.
• Pre-silicon: Work with the verification engineers to create block/system level test plans and ensure that the design is adequately covered.
• Post-silicon: Work with hardware/firmware/software engineers to resolve ASIC issues.

ASIC Design Engineer

Artificial Intelligence

• Own end-to-end performance for distributed AI workloads across multi-node clusters
• Benchmark and tune open-source & industry workloads on current and future hardware
• Design and optimize distributed serving topologies and validation efforts
• Build crisp proof points comparing Cornelis Omni-Path to competing interconnects
• Instrument and visualize performance and evangelize best practices

AI Performance Engineer

Engineering Manager

• Leading an ASIC Design Verification Team and deliver block level and full chip verification and emulation activities with high quality
• Overseeing verification test planning, execution, and the development of innovative verification methodologies
• Driving functional and code coverage closure
• Collaborating closely with RTL, architecture, software/firmware, emulation, and post-silicon validation teams
• Contributing to the development and execution of a DV strategy that aligns with the company’s objectives for first pass silicon success
• Hiring, training, and supporting a team of ASIC engineers to ensure timely and cost-effective product development
• Supporting the organizational goals through people management aspects

ASIC Verification Engineering Manager

• responsible for the verification closure of entire projects, including design modules, sub-systems, and SoCs
• drive a wide range of activities including test-planning, UVM based testbench development, regression and coverage closure
• partner and collaborate with ASIC design, emulation, system hardware and post-silicon teams
• define overall SOC level verification strategy, technical planning, direction
• enable and drive the development of UVM environments to verify RTL at block, unit, and SoC levels
• develop and execute functional tests according to verification test plans
• instrument TB for functional and code coverage and drive to closure based on the coverage metrics
• collaborate with cross-functional teams like design, software, emulation and silicon validation teams towards ensuring the highest design quality
• guidance and leadership of team members
• driving results via mentoring, coaching, and counseling
• generation and enforcement of coding and verification guidelines

Principal ASIC Verification Engineer

• Design and implement advanced Ethernet protocols for next-generation Ethernet switch ASICs, focusing on RTL development
• Develop microarchitecture specifications for Ethernet protocol blocks
• Implement Ethernet protocols such as Priority Flow Control, TCP, UDP, RoCEv2, VLAN, ECMP, DCQCN, ECN, and Security in Transmit and Receive pipelines using Verilog/System Verilog
• Collaborate with verification engineers to create block- and system-level test plans to ensure comprehensive design coverage
• Define timing constraints for RTL blocks and work with Physical Design engineers to optimize timing closure
• Support post-silicon validation, collaborating with hardware, firmware, and software teams to debug and resolve ASIC issues
• Contribute to performance optimization and power-aware design strategies for Ethernet subsystems

Senior ASIC Design Engineer

• Design and implement advanced Ethernet protocols for next-generation Ethernet switch ASICs
• develop microarchitecture specifications for Ethernet protocol blocks
• implement Ethernet protocols in Transmit and Receive pipelines using Verilog/System Verilog
• collaborate with verification engineers to create test plans
• define timing constraints for RTL blocks
• support post-silicon validation
• contribute to performance optimization and power-aware design strategies

Ethernet ASIC Design Engineer

Account Executive

• Identify, prospect and develop relationships with key end customers in the Health & Life Sciences Industry
• Formulate and execute direct sales strategies to achieve annual sales targets
• Maintain, manage, and build the sales pipeline in a CRM tool and report progress weekly
• Work closely with channel sales, partner sales and OEM teams to advance sales opportunities
• Deliver presentations of company solutions to target end customers
• Foster close collaboration with internal product, marketing, and sales teams to nurture the pipeline
• Harness the technical partner ecosystem to extend field reach and enhance customer engagement
• Offer customer and market feedback to internal product teams for continuous improvement

Senior Account Executive – Health & Life Sciences Sales

• Identify, prospect and develop relationships with key end customers in the Financial Services Industry
• Formulate and execute direct sales strategies to achieve annual sales targets.
• Identify and engage key FSI end customers and generate sales opportunities.
• Maintain, manage, and build the sales pipeline in a CRM tool and report progress weekly.
• Work closely with channel sales, partner sales and OEM teams to advance sales opportunities.
• Deliver presentations of company solutions to target end customers.
• Foster close collaboration with internal product, marketing, and sales teams to nurture the pipeline.
• Harness the technical partner ecosystem to extend field reach and enhance customer engagement.
• Offer customer and market feedback to internal product teams for continuous improvement.

Senior Account Executive – Financial Services Industry Sales

Sales Development Rep

• Perform extensive research on prospective customers, search and identify leads within those accounts and establish first contact with targeted prospects
• Manage ingest of leads from all sources, perform research to qualify those leads and determine best strategy to convert those leads into new business opportunities
• Influence demand for Cornelis Networks products through its global network of channel and OEM partners
• Define and craft sales enabling content (in partnership with marketing) including solution recipes, AI-focused industry vertical playbooks and techniques to overcome common customer objections
• Work closely with account managers, channel/partner sales and OEM teams to advance sales opportunities
• Deliver presentations of company solutions to target end customers, especially as first contact within net new logo accounts
• Foster close collaboration with internal product, marketing, and sales teams to nurture the pipeline
• Maintain accurate records and report weekly on all activities including calls, emails and research within the CRM system
• Offer customer and market feedback to internal product teams for continuous improvement
• Role carries a quota and is focused on driving sales from end customers that leverage HPC, data analytics, and AI

Sales Development Representative, HPC & AI

Manager

• Design, implement, and manage a Linux-based HPC environment with 200+ compute nodes to support ASIC development
• Oversee administration of batch compute systems including SLURM or LSF
• Manage and optimize NFS systems and clustered storage infrastructure
• Oversee observability systems (monitoring, logging, alerting)
• Drive adoption of Infrastructure as Code and automated workflows
• Implement and enforce best practices for system availability, performance tuning, capacity planning, lifecycle management
• Ensure high availability and performance of services including VNC, NFS, license servers and GitHub
• Collaborate with engineering teams to understand compute requirements and optimize infrastructure
• Lead capacity planning and infrastructure expansion initiatives
• Manage resources responsible for on-premises hardware installation, maintenance, and monitoring
• Drive adoption of AI within the infrastructure team and workflows

Senior Manager, ASIC Infrastructure

• Own pre- and post-launch performance: plan, execute, and sustain performance validation, debugging, and optimization for adapters, switches, and fabric software—first in lab, then at scale in production
• Lead performance for post-silicon bring-up validation of networking ASICs and end-products (adapters, switches, etc.); driving optimization and characterization against networking metrics and application performance
• Deliver white-glove customer support at scale: reproduce field issues, co-debug in shared/onsite labs, land mitigations and durable fixes, and publish per-customer tuning guides
• Pathfind and optimize forward-looking workloads: drive research and enablement for AI inference (QPS, P99/P99.9, cost/throughput), distributed AI training (NCCL/RCCL collectives), and traditional HPC (manufacturing, life sciences, climate)
• Multi-fabric research & enablement: evaluate and tune Cornelis/Omni-Path, Ethernet/RoCEv2, and InfiniBand across topologies (Clos/fat-tree/dragonfly), routing (ECMP/adaptive), and congestion control (credit, PFC/ECN/DCQCN)
• Explore platform designs & tunings end-to-end: CPU/GPU NUMA placement, PCIe/GPU-Direct, BIOS/firmware, PTP/1588, switch/NIC QoS & scheduling, queue depths, microburst tolerance, ECN mark rates, retransmits, fairness
• Design credible experiments: synthesize representative traffic, replay workload traces, and run on-cluster A/B tests with statistically sound comparisons (P50/P90/P99)

Principal Performance Engineer

• Execute computational fluid dynamics (CFD) and thermal simulations, including modeling, pre-/post-processing, and analysis.
• Perform thermal measurements and qualification testing; correlate empirical data with simulation results for validation.
• Develop and document design guidelines based on simulation and 3D modeling insights.
• Lead thermal design across all levels: from chip and PCB, to subsystem and chassis, up through rack and data center integration.
• Manage trade-offs between thermal performance, mechanical constraints, and cost, ensuring designs meet requirements from concept through end-of-life.
• Partner with mechanical, electrical, firmware/software, system test, and manufacturing teams to drive product readiness and move into production.
• Contribute to the definition of the thermal roadmap and drive continuous improvements in design workflows and processes across product lifecycles.

Thermal Design Engineer

Cloud Engineer

• Build and grow strategic partnerships with leading public cloud and next-generation neo-cloud providers
• Prospect new opportunities and secure sponsorship from influential stakeholders
• Align cloud technology roadmaps with Cornelis’ differentiated capabilities
• Work closely with product, sales, and marketing teams to embed Cornelis solutions in AI cloud deployments
• Hunt for new opportunities across cloud service providers and neo-cloud players by proactively identifying, engaging, and developing relationships with key influencers within each organization
• Open doors at target accounts and establish Cornelis as a trusted partner by leveraging persistence, creativity, and strong customer engagement
• Align technology roadmaps between Cornelis and cloud-native customers to influence infrastructure decisions in AI and enterprise cloud deployments
• Represent Cornelis Networks at cloud-hosted events, trade shows, executive forums, and industry conferences
• Serve as the cloud customer advocate internally, providing structured feedback to shape Cornelis’ product and market strategies
• Operate with grit and resilience, navigating complex, matrixed partner organizations to build alignment from field sellers to executive decision-makers
• Requires 50% travel to customer sites, events, trade shows and conferences