Senior Manager, ASIC Design Engineering

Cornelis Networks

Senior ASIC Design Engineering Manager at Cornelis Networks leading RTL design team. Responsible for high-performance networking ASICs development and ensuring project schedules are met in a remote environment.

Posted 7/8/2026full-timeRemote • California • 🇺🇸 United StatesSeniorWebsite

About the role

Key responsibilities & impact

Own ASIC RTL delivery schedules across major milestones by tracking, monitoring, and reporting progress against committed plans
Utilize data-driven insights to predict schedule risks and proactively reallocate human resources to keep the project on track
Align RTL delivery schedules with DV and emulation enablement and manage feedback loops and dependencies efficiently
Facilitate physical design handoffs by ensuring design teams provide high-quality RTL and constraints that minimize timing-closure iterations
Track physical design feedback and delivery schedules to support physical design signoff and tape-out milestones
Lead long-term headcount planning and organizational design for the ASIC department
Identify skill gaps and execute global talent acquisition strategies that support the product roadmap

Requirements

What you’ll need

15+ years in the semiconductor industry, preferably in high performance designs on advanced technology nodes, with at least 5 years in people management
B.S. or M.S. in Computer Engineering, Electrical Engineering, or related technical field, or equivalent practical experience
Deep understanding of the interaction between Design, Verification, Emulation, and Physical Design teams
Proven ability to lead large engineering organizations through multiple full-cycle ASIC product launches in a remote environment
Ability to coordinate across multiple projects, manage risks and escalations, and work under tight schedules and budget constraints
Strong technical expertise in microarchitecture development, RTL coding (Verilog/System Verilog), synthesis, STA/timing closure, physical design, and verification methodologies
Exposure to one or more industry standards/protocol stacks such as PCIe, Ethernet, UCIe, UALink
Demonstrated ability to optimize designs for PPA (power, performance, area) and to integrate major subsystems (interconnect, I/O, memory)

Benefits

Comp & perks

Competitive compensation package that includes equity, cash, and incentives
Health and retirement benefits
Generous paid holidays
401(k) with company match
Open Time Off (OTO) for regular full-time exempt employees
Sick time, bonding leave, and pregnancy disability leave

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills & Tools

RTL Delivery SchedulingData-Driven InsightsSynthesisSTA/Timing ClosurePhysical DesignVerification MethodologiesDesign Feedback ManagementProject CoordinationRisk ManagementTalent Acquisition Strategies

Soft Skills

LeadershipCollaborationCommunicationProblem-SolvingOrganizational Design

Certifications

B.S. or M.S. in Computer EngineeringB.S. or M.S. in Electrical Engineering