Marvell Technology

Account Manager

• Develop and implement comprehensive AI, Networking, and Custom Silicon sales strategies
• Build and maintain strong relationships with key influencers
• Understand customer pain points and effectively communicate solutions
• Collaborate closely with internal teams
• Identify, support, and manage Marvell opportunities
• Stay current with industry trends and provide valuable insights
• Prepare accurate sales forecasts and track progress
• Lead negotiations on terms and pricing to close deals

Strategic Account Manager, Sales Director

Engineer

• Collaborate with IC design, physical layout, assembly engineering, and marketing to support package planning and substrate design
• Build and correlate SI/PI models for advanced interconnects; perform 2D/3D EM simulations and generate routing, stack‑up, and decoupling guidelines
• Analyze power‑distribution networks and high‑speed signal paths from pre‑layout through post‑layout
• Perform VNA and TDR characterization of package/PCB structures and compare bench data with simulations
• Automate analysis workflows using Python (e.g., simulation sweeps, reporting, rule checks)
• Document technical results and present recommendations to cross‑functional teams
• Contribute to design reviews and support the release of package designs to manufacturing
• Use tools such as HFSS, SI‑Wave/Clarity, PowerSI, Spectre/ADS/HSpice, and APD or PADS.

Advanced Packaging Engineer – SI, PI

Full-stack Engineer

• SI/PI analysis of designs and optimization within 2D/2.5D/3D packages
• Interfacing with product design teams for optimized floor-planning, package related design input and power delivery network design
• Perform wiring studies in order to determine optimal signal routing, power delivery verification and package size determination

Advanced Packaging Staff Engineer

Mechanical Engineer

• Take ownership of one or more key digital blocks, leading the design from architecture definition through implementation
• Drive all aspects of block design, including area and timing optimization, lint, and CDC/RDC analysis
• Work closely with the verification engineers to support and contribute to block-level verification, ensuring alignment between design and verification goals

Principal Design Engineer

• Lead the design, simulation, and validation of photonic test and assembly systems, including optical probe hardware, lens assemblies, and alignment platforms.
• Develop and qualify optomechanical solutions for wafer-level and package-level optical testing, including co-packaged optics (CPO) and standalone optical engines.
• Drive BOM creation, vendor engagement, and prototype validation for optical test, including fiber assemblies, loopbacks, blind-mates, and passive optics.
• Collaborate with mechanical, thermal, automation, and product engineering teams to ensure seamless integration of photonic systems into test infrastructure.
• Define and execute evaluation plans, margining, and correlation studies for optical performance and alignment robustness.
• Support development of optical test vehicles and alignment systems for NPI and high-volume manufacturing.
• Analyze optical system performance, identify root causes of variation, and drive continuous improvement in alignment accuracy, repeatability, and throughput.

Senior Principal Photonics Engineer

Financial Planning and Analysis

• Own and execute the enterprise FP&A systems strategy aligned to Marvell’s business priorities
• Define multi-year roadmaps that support AOP, LRP, executive decision-making, and global finance transformation
• Lead a GenAI first approach to modernizing FP&A capabilities
• Identify and prioritize GenAI use cases such as predictive forecasting, scenario modeling, variance explanation, and automated executive narratives
• Establish guardrails for responsible AI adoption within Finance
• Operate and continuously enhance a global FP&A technology ecosystem
• Drive modernization of FP&A platforms including OneStream, Power BI, Databricks, and ERP integrations
• Deliver large-scale, high-impact initiatives that transform FP&A processes
• Establish best practices, operating rhythms, and governance models to improve delivery quality
• Serve as the primary IT leader and trusted partner to FP&A
• Hire, develop, and lead a global team of FP&A systems professionals
• Optimize total cost of ownership while ensuring service quality and risk mitigation
• Oversee portfolio delivery and executive reporting

Director – FP&A Systems

Software Engineer

• Design, develop, and maintain high-performance Linux kernel network device drivers
• Integrate and maintain Linux Traffic Control (TC) frameworks with hardware-based packet processing and offload pipelines
• Develop and tune packet scheduling, shaping, policing to meet performance and QoS requirements
• Contribute code, bug fixes, and enhancements to the Linux kernel, with an emphasis on upstream-quality submissions and long-term maintainability
• Collaborate on U-Boot and firmware development for ARM-based SoCs to support networking and platform bring-up requirements
• Work closely with cross-functional teams including silicon, firmware, QA, and system software teams to deliver end-to-end networking solutions
• Participate in design reviews, code reviews, and technical discussions across distributed teams
• Apply strong analytical and problem-solving skills to diagnose complex system-level issues and drive effective solutions.

Firmware Developer – ARM64, C, Ethernet, L2/L3 Networking Protocols

Director

• Lead and mentor a strong SOC design team across multiple geographies
• Work closely with various stakeholders to architect and design high quality SOC designs
• Lead the SOC design team by being hands-on with RTL coding, IP integration flows and drive quality and methodology improvements
• Define, track and drive project execution timelines and milestones working closely with various stakeholders and program management for successful product execution
• Define the system architecture, micro-architecture and register specification for highly complex SoCs and participate in specification writeup
• Work with the physical design teams, providing guidance and support in floorplanning, power analysis, synthesis and timing signoff through reviews and design changes
• Work with the verification team on pre-silicon verification tasks such as reviewing the verification test plans, coverage analysis, full-chip simulation and emulation, performance and power analysis and debug
• Work with third party vendors to define customization requirements of third party IPs (controller, PHY, etc.)
• Conduct detailed performance, architectural and design requirement reviews with cross-functional teams, IP Vendors and customers
• Recruit, retain, and develop top engineering talent

Director, SOC Design

• As a member of the DFX team, you will be responsible for major DFX disciplines execution (ATPG, MBIST, DFX Verification, STA sign off) and post si activities.
• In this role you will act as DFX owner for the whole project or major DFX disciplines and will work closely with SoC Architecture, Design, Verification, Backend and post-silicon teams, taking into account all aspects of ASIC flow and full range of pre-Si and post Si activities.