Marvell Technology

Designer

• Own end-to-end verification of PCIe (Gen6/Gen7) and CXL (3.0/4.0) subsystems, from test planning through coverage closure and signoff
• Define and execute comprehensive verification plans based on protocol specifications and micro-architecture requirements
• Architect and develop scalable UVM/System Verilog testbenches for PCIe/CXL controllers and fabric-level subsystems
• Integrate and configure PCIe/CXL VIP for subsystem and system-level verification environments
• Validate CXL.io, CXL.cache, and CXL.mem protocols, including coherency and memory semantics across complex flows
• Develop constrained-random and directed test suites to achieve high functional coverage across corner and stress scenarios
• Debug complex failures such as protocol violations, ordering issues, and coherency bugs using waveforms, logs, and protocol analyzers
• Implement System Verilog Assertions (SVA) for protocol compliance, improving early bug detection and debug efficiency
• Drive functional, code, and assertion coverage closure, identifying gaps and developing targeted tests to meet signoff goals
• Validate performance metrics (latency, throughput, QoS) under high-bandwidth and stress workloads
• Develop automation (Python/Shell) for regression management, log triage, and coverage reporting, improving productivity
• Collaborate with design, architecture, firmware and validation teams, influencing design-for-verification and mentoring junior engineers

Senior Staff Design Verification Engineer – PCIE/CXL Sub-System

Full-stack Engineer

• Develop and validate timing constraints for intricate SoC designs
• Collaborate with Architecture, RTL, DFT, and Analog teams to understand the design requirements, analyze the timing complexities, and develop consolidated timing modes and constraints for synthesis, PnR and chip timing sign-off flows
• Own and contribute to various Front-End Implementation tasks & flows like Synthesis, UPF development, Logical Equivalence Checks (LEC), Functional ECOs, etc.
• Analyze and understand the tradeoffs between power/performance and area goals to drive them into overall chip implementation flows
• Perform Physical Aware Synthesis using industry-standard tools like Fusion Compiler
• Resolve or find workarounds for tool issues, independently or working with EDA tool vendors
• Automate Front End Flows and processes using scripting languages such as Tcl or Python
• Ensure compliance with Netlist Handoff checklists and criteria for delivery to PD
• Document best practices and lessons learned to drive continuous improvements in future projects

Senior Staff Engineer, ASIC/VLSI Synthesis and Design

• Orchestrate end-to-end integration and delivery of complex infrastructure programs, enforcing development schedules and performance targets to ensure successful on-time technology transition to HVM teams
• Drive technical milestones for new test hardware development, with a special focus on the deployment of Known Good Die (KGD), Co-Packaged Optics (CPO), and Co-Packaged Copper (CPC) solutions
• Act as a central integration point between specialized Thermal, Mechanical, Photonic, and Signal Integrity/Power Integrity teams as the primary lead to deliver unified, high-performance hardware and test solutions
• Collaborate with cross-functional teams across Design, Packaging, Operations, and Quality organizations to align new infrastructure capabilities with future product requirements
• Capture and translate customer future roadmaps and specifications into actionable internal engineering roadmaps and technology readiness schedules
• Strengthen new and existing partner relationships and jointly drive long-term technical roadmaps for manufacturing and test hardware to ensure Operations readiness for rapid scaling requirements
• Drive transfer-to-manufacturing protocols, evaluating and qualifying new partners and managing the global deployment of test architectures from wafer sort through system-level test
• Own comprehensive project schedules, track critical path deliverables, and proactively implement risk mitigation frameworks
• Represent advancements at industry conferences and technical forums to communicate Marvell infrastructure vision and technical leadership
• Monitor industry trends in advanced packaging, photonics, and high-speed signaling to ensure internal manufacturing infrastructure remains at the cutting edge
• Optimize solutions for manufacturing yield, repeatability, and throughput by providing direct technical feedback on mechanical, thermal, photonic, signal integrity, and power integrity performance on test vehicles.

Senior Principal Engineer, Manufacturing Infrastructure

Engineer

• Be the key driver of the end-to-end development of Celestial’s external light source technology, from concept to volume manufacturing
• Responsibilities would include full life-cycle support of the light sources, from initial design selection/development, procurement and full characterization to reliability qualification and production release
• Act as the main point of contact with various vendors to enable the completion of all the above milestones, and also resolve any performance/yield/supply issues
• Work cross-functionally with systems, packaging, firmware, manufacturing, quality, and supply chain teams to deliver production-ready solutions
• Contribute to the development of other external optical components and fiber sub-assemblies used in Celestial products

Principal Optical Engineer – Light Sources

Account Executive

• Provide critical support in forecasting revenue and managing the sales design funnel, ensuring accurate and timely projections
• Design, implement, and validate operational dashboards and KPIs to measure sales productivity
• Analyze and provide insights for resource allocation, optimizing pipeline management while maintaining expense targets
• Execute complex data analyses on pipeline management, conversion ratios, and cycle times
• Produce comprehensive executive summaries and actionable recommendations to inform strategic decisions
• Manage multiple projects and ad-hoc requests simultaneously in a fast-paced environment with shifting priorities
• Provide actionable recommendations through deep analysis that supports key business decisions
• Develop expert knowledge of in-house data sources, quickly extracting and analyzing data to drive decision-making
• Provide ongoing account management support, working closely with sales teams to ensure client satisfaction and retention
• Work closely with Sales, Marketing, Finance & IT to enhance reporting and tracking systems
• Lead training sessions for Sales and Marketing users on new systems, tools, and best practices.

Inside Sales Representative

• SI/PI analysis of designs and optimization within 2D/2.5D/3D packages
• Interfacing with product design teams for optimized floor-planning, package related design input and power delivery network design
• Perform wiring studies to determine optimal signal routing, power delivery verification and package size determination
• Documenting analysis results and present findings to internal teams
• Participating in cross-functional meetings and design reviews
• Taking ownership of assigned tasks and following through to completion, adjusting approach as needed to meet goals

Advanced Packaging SI/PI Staff Engineer – Early Career

Frontend Engineer

• Develop and maintain leading-edge CAD flows addressing the needs of Marvell’s various Business Units.
• Contribute to the deployment and support of highly modular and automated CAD flows.
• Work in collaboration with the infrastructure and flow teams to ensure optimal integration within the overall CAD platform.
• Come-up with innovative solutions to ever-increasing design challenges.
• Drive stakeholders' alignment across multiple BUs over key CAD architectural decisions.

Front End CAD Principal Engineer

Program Manager

• Lead custom solution programs for hyperscale cloud data center customers
• Own the complete program lifecycle: initiation, planning, execution, and closure
• Drive execution across development, validation, qualification, sample delivery, and production release phases
• Monitor and control program performance to maintain alignment with schedule, quality, and cost targets against the Plan of Record (POR)
• Collaborate across a matrixed organization, engaging engineering, operations, and business teams to ensure program success
• Serve as the primary point of contact for internal and external communications at engineering, management, and executive levels
• Proactively identify risks and lead mitigation planning
• Escalate and resolve issues effectively to maintain program momentum

Principal Program Manager – Hyperscaler Cloud Data Center, Full Lifecycle Program Ownership

• Develop packaging technology roadmap for AI XPU, XPU-attach and Switch
• Explore technologies beyond what is currently available, make recommendations, and create and protect IP to maximize performance.
• Create new package technology concepts from open ended ideas, perform routing feasibility, signal and power integrity studies for design optimization.
• Explore technology feasibility and create proof-of-concept samples and productize technologies.
• Define package architecture including chiplet topology, interposer/substrate scaling, power delivery network strategy, and thermal design envelope.
• Lead co-design efforts across silicon design, floorplanning, PDN modeling, and mechanical/thermal reliability.
• Lead package material selection, substrate stack-up definition, mechanical modeling, and reliability analysis.
• Partner with silicon design teams to co-optimize die floorplan, bump map, TSV, and RDL requirements.
• Work with OSATs / Foundry partners to evaluate process capability, manufacturability, yield, and cost.
• Drive package qualification and reliability validation to volume readiness.

Distinguished Engineer, Advanced Package Technology

Implementation Specialist

• Architect and lead the development of next-generation physical design methodologies and automation flows for Complex SubSystems
• Provide deep technical leadership in RTL-to-GDSII implementation, including synthesis, floor planning, place and route, clock tree synthesis, and timing closure
• Hands on work on complex Subsystem hardening
• Working with Senior and Junior engineers to deliver reference floorplan, fully synthesized, timing closed Sub System partitions to SOC team
• Work with DFT team and SOC team for DFT insertion and closing timing at SOC level
• Work with RTL team to close timing, ECOs, Bug fixes etc
• Serve as a key technical advisor across multiple projects, influencing design decisions and resolving complex implementation challenges
• Collaborate with global cross-functional teams, including RTL, verification, and CAD, to ensure cohesive and optimized design execution.
• Mentor and coach senior and junior engineers, fostering technical growth and promoting best practices across the organization
• Evaluate and drive adoption of emerging EDA tools and technologies in partnership with internal CAD and external vendors
• Represent the physical design team in strategic technical discussions with internal and external stakeholders, contributing to roadmap planning and methodology evolution

Principal Physical Design – Implementation Engineer

• Develop network topology discovery and visualization for rack‑ and data‑center‑scale environments
• Architect telemetry collection from switches, NICs, and optical modules
• Correlate L1/L2 telemetry to monitor link health and diagnose failures
• Support scale‑up and scale‑out AI cluster networking
• Model interactions between ToR/spine switches, NICs, optics, and servers
• Monitor Ethernet switching, routing behavior, and link state changes
• Analyze AI/ML traffic patterns and collective communication behavior
• Integrate with customer network management systems and data platforms
• Develop Python tools for telemetry ingestion, processing, and diagnostics
• Build APIs/SDKs for topology management and link monitoring
• Automate network validation, compliance checks, and diagnostics
• Support streaming telemetry integrations
• Collaborate with firmware, hardware, and DevOps teams on telemetry requirements
• Support customer integrations and architecture discussions
• Lead network telemetry architecture decisions
• Act as subject‑matter expert for data center networking

Senior Staff Software Engineer – Embedded System Level Firmware, BGP, OSPF, VXLAN, EVPN, SDN, network virtualization

• Build complex Subsystem emulation models, including design integration, environment setup, compilation, and debug across industry-leading platforms (e.g., Veloce, ZeBu, Palladium)
• Drive emulation bring-up activities, including clock/reset sequencing, firmware boot, and system validation using pre-silicon hardware models
• Execute emulation test plans to support verification, performance analysis, software development, and system validation needs across multiple teams
• Collaborate closely with Senior Emulation Engineers, RTL design, verification, and firmware teams to develop accurate hardware models, and ensure seamless integration into the emulation environment
• Debug complex SoC and subsystem issues across RTL, firmware, emulation platforms, and toolchain interactions
• Optimize emulation performance, including model partitioning, timing, and runtime efficiency
• Automate flows and improve productivity through scripting (Python, Perl, Tcl, shell) and tooling enhancements
• Interface with EDA vendors (Synopsys, Cadence, Siemens) to evaluate tool capabilities, resolve technical issues, and drive feature improvements

Senior Staff Emulation Engineer

• Lead the development of complex SubSystem emulation models, including design integration, environment setup, compilation, and debug across industry-leading platforms (e.g., Veloce, ZeBu, Palladium)
• Drive emulation bring-up activities, including clock/reset sequencing, firmware boot, and system validation using pre-silicon hardware models
• Create and execute emulation test plans to support verification, performance analysis, software development, and system validation needs across multiple teams
• Collaborate closely with RTL design, verification, and firmware teams to define requirements, develop accurate hardware models, and ensure seamless integration into the emulation environment
• Debug complex SoC and subsystem issues across RTL, firmware, emulation platforms, and toolchain interactions
• Optimize emulation performance, including model partitioning, timing, and runtime efficiency
• Automate flows and improve productivity through scripting (Python, Perl, Tcl, shell) and tooling enhancements
• Interface with EDA vendors (Synopsys, Cadence, Siemens) to evaluate tool capabilities, resolve technical issues, and drive feature improvements

Principal Emulation Engineer

Mechanical Engineer

• Building next-generation 50G/100G optical link solutions for data-centric computing
• Architecting and implementing high-speed analog and mixed-signal circuits for photonic transceivers and electronic ICs (EICs)
• Collaborating with a multidisciplinary team across photonics, system, packaging, and validation to deliver scalable, low-power, high-performance EICs for optical compute and interconnects
• Conducting top-down architectural analysis of AMS systems
• Enhancing system performance using digitally assisted analog techniques and appropriate partitioning of analog and digital circuits
• Driving transistor-level feasibility studies for various AMS circuits
• Defining design specifications and verification plans
• Defining production and bench-level test plans

Senior Staff Design Verification Engineer – PCIE/CXL Sub-System

Senior Staff Design Verification Engineer – PCIE/CXL Sub-System

Senior Staff Engineer, ASIC/VLSI Synthesis and Design

Senior Principal Engineer, Manufacturing Infrastructure

Principal Optical Engineer – Light Sources

Inside Sales Representative

Advanced Packaging SI/PI Staff Engineer – Early Career

Front End CAD Principal Engineer

Principal Program Manager – Hyperscaler Cloud Data Center, Full Lifecycle Program Ownership

Distinguished Engineer, Advanced Package Technology

Principal Physical Design – Implementation Engineer

Senior Staff Software Engineer – Embedded System Level Firmware, BGP, OSPF, VXLAN, EVPN, SDN, network virtualization

Senior Staff Emulation Engineer

Principal Emulation Engineer

Principal Analog/Mixed-Signal Design Engineer