Intel Corporation

Mechanical Engineer

• Drive end-to-end development for silicon packaging substrate design from concept through tapeout
• Perform substrate fit and routing studies to assess design, performance, and cost tradeoffs
• Implement physical layout and routing of package designs, ensuring adherence to design rules
• Optimize silicon-package-board performance and pinout by working closely with silicon and hardware teams
• Define substrate design rules and conduct internal and external design reviews
• Analyze data and resolve design rule checks (DRCs) to refine package designs
• Develop comprehensive documentation and collateral, storing them in the product lifecycle management system of record

Silicon Packaging Design Engineer

Solutions Engineer

• Own and drive thermal architecture end‑to‑end, translating advanced silicon capabilities into practical, production‑ready system solutions
• Lead thermal architecture definition and execution across the full product lifecycle from early concept exploration through production and HVM
• Co‑design innovative cooling solutions with top OEM partners, directly influencing high‑volume consumer and commercial PC products
• Define power and temperature constraints based on real system cooling capabilities, and deliver clear guidance to product, platform, and manufacturing teams with a portfolio of thermal solutions
• Perform thermal analysis, modeling, and validation for air‑ and liquid‑cooled systems across notebooks, desktops, and emerging form factors
• Apply deep expertise in heat transfer fundamentals conduction, convection (active and passive), and radiation to guide design tradeoffs for high density form factors
• Characterize and validate cooling technologies, including heat sinks, fans, heat pipes, vapor chambers, cold plates, and TIMs
• Develop and correlate multi‑scale thermal models spanning silicon, package, PCB, and full system levels
• Tune system‑level thermal management, integrating mechanical design, firmware‑based thermal policies, and platform controls
• Deliver technical leadership and design reviews in collaboration with pre‑silicon, post‑silicon, and validation teams
• Partner closely with power, mechanical, electrical, reliability, and manufacturing teams to solve complex, cross‑disciplinary challenges
• Drive continuous innovation through experimentation, prototyping, research, and data‑driven analysis

Senior Thermal Solutions Architect – Client Platforms

Full-stack Engineer

• Designs, develops, tests, and debugs software tools, flows, and methodologies used in design automation and by teams in the design of hardware products, process design, or manufacturing.
• Capturing user stories/requirements, writing both functional and test code, automating build and deployment, and/or performing unit, integration, and end-to-end testing of the software tools.

EDA Tools Software Engineer

• Develop RTL code and implement optimized logic designs for GPU IPs, ensuring alignment with architecture and microarchitecture specifications
• Perform power, performance, area, and timing optimization to meet design goals during physical implementation
• Participate in defining architecture and microarchitecture features for GPU blocks, contributing to innovation and technology leadership
• Execute unit-level verification, debug failing RTL tests, and resolve design issues to achieve correctness, functionality, and robustness at all verification hierarchies
• Utilize formal equivalence verification (FEV) techniques to ensure design accuracy and fidelity across development stages
• Collaborate with SoC customers to ensure seamless and high-quality integration of GPU blocks into full chip designs
• Drive microarchitecture-level enhancements and provide technical documentation to support design and development activities
• Explore the opportunity to shape the future of graphics design at Intel.

GPU Logic Design Engineer

Engineer

• Contribute to the design, development, and enhancement of tools supporting engineering workflows, including compilers, debuggers, profilers, and build systems.
• Assist in toolchain integration, performance analysis, and feature development to improve developer productivity.
• Collaborate with cross-functional teams to align tool capabilities with evolving platform requirements.
• Analyze and debug technical issues, identify root causes, and implement solutions.
• Apply system-level thinking and engineering fundamentals to solve complex problems.
• Learn and integrate new tools and technologies to enhance your technical skillset.
• Participate in team meetings and contribute to collaborative project goals.

Density Fill Development Engineer Intern

• Join our team as a Software Performance Engineer and contribute to innovative solutions that enhance application efficiency across modern computing platforms.
• Design, develop, analyze, debug, optimize, integrate, tess, and/or validate existing or new device drivers software, including the design and implementation of platform level features that encompass interfacing with drivers to higher level frameworks.
• Research and collaborate with other engineers and architects in the design, development, integration, and/or validation of device drivers on the target OS.
• Working with cross-functional teams, you will deliver solutions that maximize hardware potential through advanced optimization techniques.
• Design and develop software frameworks to optimize application workloads.
• Implement code analysis and performance enhancement algorithms.
• Collaborate with architects and engineers to integrate optimization solutions.
• Analyze application behavior and identify performance improvement opportunities.
• Develop and maintain optimization tools and runtime systems.
• Validate and benchmark performance improvements.
• Apply debugging and profiling techniques to enhance code quality.
• Deliver software solutions following established development practices.

Software Engineer

• Own and drive roadmap requirements aligned to business objectives, device strategies, market needs, and technology readiness
• Translate industry trends, customer insights, regulatory considerations, and internal constraints into clear roadmap priorities and tradeoffs
• Partner closely with product management, engineering, and architecture teams to ensure feasibility, dependency management, and alignment with platform strategies
• Support annual and quarterly planning cycles by developing roadmap narratives, options, and scenario analyses for leadership decision making
• Identify portfolio gaps, overlaps, and risks, and proactively drive alignment and prioritization discussions across stakeholders
• Partner with device architects and technical leads to shape future state solutions and articulate the art of the possible for priority customers and use cases
• Act as a bridge between market requirements and internal execution, ensuring solutions are grounded in real-world deployment constraints
• Develop solution positioning, value propositions, and high-level capability definitions in collaboration with technical and business stakeholders
• Support priority customer, partner, and ecosystem engagements by clearly articulating solution direction, roadmap alignment, and differentiation
• Ensure learnings and feedback from customer engagements, pilots, and deployments are systematically fed back into roadmap evolution

Health and Life Sciences Systems Engineer

• Provide executional leadership across a complex U.S. domestic tax compliance and filing environment
• Drive compliance execution through effective planning, coordination, and follow through
• Identify, frame, and take ownership of judgment driven U.S. domestic tax issues
• Evaluate facts, data, and technical considerations
• Translate technical decisions into clear execution guidance
• Ensure resolved positions and process improvements are sustained over time
• Contribute to continuous improvement of compliance processes, controls, and documentation

Senior Manager, U.S. Domestic Tax Compliance

• building strong foundations in AI software stacks
• GPU programming
• performance optimization
• design, development, and optimization of AI software solutions
• algorithms, frameworks, and AI software architectures across domains
• implementing and tuning models for performance and accuracy
• applied research
• hardware software integration
• creating AI software solutions in partnership with internal product teams and external partners
• system level deployment to enable scalable and efficient AI solutions
• hands on experience and projects that support Intel business goals in a collaborative environment

AI Software Engineering Intern

Product Manager

• Own product supply health and messaging guidance for assigned product lines, ensuring optimal supply-demand balance
• Drive comprehensive product supply strategy development and execution with cross-functional teams for new product introductions, end-of-life planning, and roadmap SKU offerings
• Determine strategic geo/customer supply allocation through weekly, monthly, and out-of-cycle planning processes
• Establish monthly build strategies at both family and vertical market levels
• Proactively manage supply chain operations to prevent excess inventory and optimize working capital
• Partner with platform and component teams to execute relationship and functional analyses that enhance supply chain efficiency
• Build, maintain, and optimize reports related to supply support and utilization tracking for critical business operations
• Lead cross-functional collaboration with manufacturing, sales, and product teams to align objectives and streamline processes
• Provide comprehensive training on sales operations processes, tools, and procedures to enhance team capabilities

Server Product Manager

• Define and drive the technical vision, architecture, and roadmap for Intel's neuromorphic runtime software stack
• Architect, develop, and optimize firmware and runtime components
• Architect and deliver performance infrastructure
• Integrate the runtime stack into existing robotics and edge software ecosystems
• Collaborate with hardware, compiler, systems, application, and solution teams to translate platform and workload requirements into robust software capabilities
• Provide technical leadership across the runtime area

Senior AI Software Architect – Runtime

Designer

• Perform chip/block-level timing analysis and optimization for IP
• Generate and verify timing constraints, conducting timing rollups for efficient physical design processes.
• Design and optimize power and performance-efficient clock networks, ensuring adherence to product requirements.
• Develop and refine methodologies for high-quality timing models to streamline physical design workflows.
• Define process, voltage, and temperature (PVT) conditions for timing analysis based on operating conditions and product binning plans.
• Collaborate with architecture, clock design, and logic design teams to develop integration workflows and validate clock network guidelines.
• Work closely with backend design teams for clock balance, timing corrections, power delivery, and partitioning strategies.
• Conduct noise glitch and signal integrity analysis, ensuring design robustness under diverse conditions.
• Contribute to tools, flows, and methodology (TFM) development to support efficient implementation and optimization processes.

Physical Design Timing Engineer

• Develops the logic design
• register transfer level (RTL) coding
• simulation
• provides DFT timing closure support
• test content generation and delivery to manufacturing for various DFx content
• participates and collaborates in the definition of architecture and microarchitecture features
• develops HVM content for rapid bring up and ramp to production on the automatic test equipment (ATE)
• applies various strategies
• tools
• and methods to write and generate RTL and structural code to integrate DFT
• optimizes logic to qualify the design to meet power
• performance
• area
• timing
• testcoverage
• DPM
• and testtime/vectormemory reduction goals and ensures design integrity for physical implementation
• reviews the verification plan and drives verification of the DFT design to achieve desired architecture and microarchitecture specifications
• collaborates with post silicon and manufacturing team to verify the feature on silicon
• supports debug requirements
• drives high test coverage through structural and specific IP tests to achieve the quality and DPM objectives of the product

Experienced DFT ATPG Engineer

Frontend Engineer

• Drive and generate Foundry's five-year PNL forecast and NPV valuation
• Track progress to BOD commitments
• Identify opportunities and required business changes to improve financial performance
• Develop what-if scenarios to assess potential impacts
• Track key financial metrics, identifying trends, and analyzing variances
• Support ad-hoc LRP requests and critical business decision making

Senior Front End Long Range Capacity Planning Analyst

• Play a pivotal role in ensuring Intel's cutting-edge products perform seamlessly
• Shape the future of technology by driving exceptional system-on-chip (SoC) debug solutions
• Collaborate with cross-disciplinary teams and influence technical direction across Intel
• Develop solutions fundamental to delivering high-quality products to market
• Perform low-level and complex debug across multiple systems, subsystems, or SoC levels for Intel products
• Develop validation plans and execute tests for multiple domain- and system-level features/flows in the SoC
• Develop and implement techniques for faster SoC and platform-level debug while isolating failing system components
• Utilize design-for-debug (DFD) tools and scripts to continuously improve debug discipline
• Conduct root cause analysis, resolve triage failures and marginality issues, and track SoC debug progress
• Collaborate with design, system validation teams, and high-volume manufacturing factories to characterize new device features and functionalities