Experienced DFT ATPG Engineer

Intel Corporation

DFT ATPG Engineer developing logic design and providing DFT timing closure support for manufacturing. Collaborating on architecture features and optimizing design for production quality.

Posted 4/28/2026full-timeBeaver Brook • California, Massachusetts • 🇺🇸 United StatesMid-LevelSenior💰 $105,650 - $200,340 per yearWebsite

About the role

Key responsibilities & impact

Develops the logic design
register transfer level (RTL) coding
simulation
provides DFT timing closure support
test content generation and delivery to manufacturing for various DFx content
participates and collaborates in the definition of architecture and microarchitecture features
develops HVM content for rapid bring up and ramp to production on the automatic test equipment (ATE)
applies various strategies
tools
and methods to write and generate RTL and structural code to integrate DFT
optimizes logic to qualify the design to meet power
performance
area
timing
testcoverage
DPM
and testtime/vectormemory reduction goals and ensures design integrity for physical implementation
reviews the verification plan and drives verification of the DFT design to achieve desired architecture and microarchitecture specifications
collaborates with post silicon and manufacturing team to verify the feature on silicon
supports debug requirements
drives high test coverage through structural and specific IP tests to achieve the quality and DPM objectives of the product

Requirements

What you’ll need

BS EE/CE or related STEM field with 3+ years of relevant DFT experience
OR MS EE/CE or related STEM field with 1+ years of relevant DFT experience
1+ years of experience in tools like Siemens Tessent
Spyglass
Fusion compiler
and/or VCS
1+ years of experience with scan insertion
low coverage debug
GLS debug
and/or post silicon debug

Benefits

Comp & perks

competitive pay
stock bonuses
benefit programs which include health
retirement
vacation

ATS Keywords

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Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard Skills & Tools

RTL codingDFT timing closuretest content generationHVM content developmentlogic optimizationverification plan reviewscan insertionlow coverage debugGLS debugpost silicon debug

Soft Skills

collaborationcommunication

Certifications

BS EEBS CEMS EEMS CE