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Silicon Packaging Design Engineer
Intel CorporationSilicon Packaging Design Engineer driving end-to-end silicon packaging substrate development for Intel. Collaborating with teams to optimize silicon package board performance and pinout.
Posted 5/1/2026full-timePhoenix • Arizona, Oregon • 🇺🇸 United StatesMid-LevelSenior💰 $141,910 - $200,340 per yearWebsite
Tech Stack
Tools & technologiesPython
About the role
Key responsibilities & impact- Drive end-to-end development for silicon packaging substrate design from concept through tapeout
- Perform substrate fit and routing studies to assess design, performance, and cost tradeoffs
- Implement physical layout and routing of package designs, ensuring adherence to design rules
- Optimize silicon-package-board performance and pinout by working closely with silicon and hardware teams
- Define substrate design rules and conduct internal and external design reviews
- Analyze data and resolve design rule checks (DRCs) to refine package designs
- Develop comprehensive documentation and collateral, storing them in the product lifecycle management system of record
Requirements
What you’ll need- Bachelor’s degree in Electrical Engineering, Mechanical Engineering, Materials Science, or Physics with 4+ years of experience
- Or Master's degree in Electrical Engineering, Mechanical Engineering, Materials Science, or Physics with 3+ years of experience
- Or Phd degree in Electrical Engineering, Mechanical Engineering, Materials Science, or Physics
- Experience with Package or board design and review tools like Siemens Xpedition, Cadence Allegro Package Design, Valor NPI, AutoCAD, or SolidWorks
- Expertise in Package Design and Development, interconnect methodologies, and/or manufacturability principles
- Familiarity with microelectronic package electrical modeling and simulation tools such as PowerDC, HyperLynx, Q3D, and HFSS
- Experience with scripting using Python, VB, C, or similar languages
Benefits
Comp & perks- competitive pay
- stock bonuses
- health insurance
- retirement plans
- vacation
ATS Keywords
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Hard Skills & Tools
silicon packaging substrate designsubstrate fit and routing studiesphysical layout and routingdesign rule checks (DRCs)package design and developmentinterconnect methodologiesmanufacturability principlesscriptingPythonC
Certifications
Bachelor's degree in Electrical EngineeringBachelor's degree in Mechanical EngineeringBachelor's degree in Materials ScienceBachelor's degree in PhysicsMaster's degree in Electrical EngineeringMaster's degree in Mechanical EngineeringMaster's degree in Materials ScienceMaster's degree in PhysicsPhD in Electrical EngineeringPhD in Mechanical Engineering