Delos Data

Mechanical Engineer

• Design and implement RTL for complex digital subsystems using Verilog/SystemVerilog
• Translate architectural specifications into clean, efficient, and scalable microarchitectures
• Collaborate with architecture, verification, and physical design teams to ensure design correctness and closure
• Develop high-quality, reusable RTL with strong coding standards and documentation
• Perform linting, CDC analysis, and ensure synthesis readiness of designs
• Support integration and debug of RTL in simulation and early silicon environments
• Participate in design reviews and provide technical input on architecture and implementation tradeoffs
• Work with verification teams to ensure comprehensive functional coverage
• Assist in timing closure and support backend teams as needed
• Contribute to continuous improvement of design methodologies, flows, and tools

RTL Design Engineer