Principal Power Design Engineer

Delos Data

Principal Power Design Engineer responsible for designing power delivery systems that support high-performance AI hardware. Overseeing component selection, schematic design, and lab validation.

Posted 7/6/2026full-timePalo Alto • 🇨🇦 CanadaLead💰 CA$160,000 - CA$240,000 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in hardware schematic design and validation for high-current power delivery systems, with a focus on multi-phase DC-DC regulators and board-level power delivery networks. Proficient in collaborating with cross-functional teams to ensure optimal power performance and reliability in complex computing platforms.

Highest-signal resume keywords

High-Current DC-DC Regulator DesignBoard-Level Power Delivery Network ImplementationLab Validation SkillsSchematic Capture and Layout OversightSPICE-Based Circuit Simulation

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Multi-Phase Buck Regulator DesignPower Sequencing CircuitryDecoupling StrategyTransient Response AnalysisVoltage RegulationLoop Stability TestingVRM Efficiency CharacterizationDC IR Drop MeasurementPower Supply Noise MitigationHigh-Speed Lane Debugging

Soft Skills

CollaborationProblem-SolvingAttention to Detail

Tools & Technologies

Cadence AllegroConceptOscilloscopeElectronic LoadNetwork AnalyzerThermal Camera

Industry Keywords

Power Hardware DesignHigh-Power ASICsGPUsProcessorsAcceleratorsPower Delivery Requirements

Tech Stack

Tools & technologies

Ruby on Rails

About the role

Key responsibilities & impact

Own hardware schematic design for multi-phase buck regulators, point-of-load converters, and power sequencing circuitry.
Select critical power components, including passives, inductors, power stages, controllers, and supporting circuitry.
Define placement and routing constraints for board-level power delivery networks, including decoupling capacitor strategy and high-current power paths.
Work closely with package engineering to ensure clean power delivery handoff at the socket or package interface.
Lead lab validation of power subsystems, including VRM efficiency, loop stability, DC IR drop, thermal behavior, and transient response.
Use oscilloscopes, electronic loads, network analyzers, thermal cameras, and related lab equipment to characterize power rails under maximum dynamic load conditions.
Partner with SI/PI engineers to measure and mitigate power supply noise and Power Supply Induced Jitter on sensitive high-speed lanes.
Debug power integrity issues across board, package, silicon, firmware, workload, and system-level interactions.
Contribute to design guidelines, validation plans, and best practices for power delivery across the company’s hardware platforms.

Requirements

What you’ll need

Extensive experience designing high-current, multi-phase DC-DC regulators for high-power ASICs, GPUs, processors, accelerators, or similar compute platforms.
Strong background in power hardware design for systems with 500W+ devices or comparable high-current power delivery requirements.
Deep understanding of board-level PDN implementation, decoupling strategy, power sequencing, transient response, and voltage regulation.
Hands-on experience with schematic capture and layout oversight for complex power delivery systems, preferably using tools such as Cadence Allegro or Concept.
Strong lab validation skills using electronic loads, oscilloscopes, network analyzers for loop stability testing, thermal cameras, and related power measurement equipment.
Experience characterizing VRM efficiency, bode plots, DC IR drop, ripple, noise, and transient behavior under dynamic workloads.
Proficiency with SPICE-based time-domain circuit simulation or similar power simulation workflows.
Ability to collaborate closely with SI/PI, package, hardware, firmware, and systems teams in a fast-moving engineering environment.

Benefits

Comp & perks

meaningful equity
benefits
401k