
SOC Memory Architect
Samsung Electronics
full-time
Posted on:
Location Type: Hybrid
Location: California • Texas • United States
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Salary
💰 $221,700 - $364,800 per year
Tech Stack
About the role
- As a SoC Memory Architect, you will play a key role in shaping the future of our premium chipsets by defining and driving the development of innovative SoC memory and cache subsystems.
- You identify, propose, and deliver new SoC memory architectures and features for premium mobile and related product platforms.
- You contribute to high-impact deliverables, with the freedom to experiment and explore novel ideas to challenge existing norms and push the boundaries of what is possible.
- You create detailed designs and specifications for memory subsystems, including memory interfaces, controllers, and caches.
- You analyze PPA trade-offs and optimize memory subsystem performance, power consumption, and area utilization to meet system requirements.
- You work closely with software, hardware, and validation teams to ensure memory subsystem designs meet system requirements and are properly integrated
- You create and maintain detailed documentation of memory subsystem designs, including architecture, implementation, and verification plans.
- You inspire high performance, mentor junior engineers, foster trust, and promote a culture of ownership culture and open communications.
- You stay up-to-date with emerging memory technologies and recommend their adoption in SoC designs.
Requirements
- 20+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 18+ years of experience with a Master’s Degree, or 16+ years of experience with a PhD
- Extensive experience designing and developing complex digital systems and SoC memory architectures.
- Expertise in memory hierarchies, memory interfaces (e.g., DDR, LPDDR, HBM), and memory controllers is crucial.
- Detailed knowledge of cache subsystems including caching policies and understanding the tradeoffs of latency, bandwidth and hierarchies
- Experience with cache coherence protocols and bus protocols – CHI/ACE/AXI
- Knowledge of memory scheduling, bandwidth management, and latency optimization.
- High familiarity with existing and emerging JEDEC memory standards
- Strong written and verbal communication skills
- Experience with the Android ecosystem and analysis tools is a plus
- Experience with Arm architecture and ecosystem is a plus
Benefits
- medical
- dental
- vision
- life insurance
- 401(k)
- free onsite lunch
- employee purchase program
- tuition assistance (after 6 months)
- paid time off
- student loan program
- wellness incentives
Applicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard Skills & Tools
SoC memory architecturememory interfacesmemory controllerscache subsystemscache coherence protocolsbus protocolsmemory schedulingbandwidth managementlatency optimizationPPA trade-offs
Soft Skills
mentoringcommunicationteam collaborationinnovationleadershiptrust buildingownership culture