Powerlattice Inc

Mechanical Engineer

• Design and develop core analog and mixed-signal circuit blocks, including bandgap references, oscillators, LDOs, op-amps, ADCs, and DACs
• Translate system and block-level specifications into robust circuit architectures and implementations
• Perform schematic capture, simulation, and optimization to meet performance, power, area, and reliability targets
• Provide layout guidance and collaborate closely with layout engineers to ensure design intent is met
• Perform post-layout (PEX) simulations and correlations with pre-layout analysis
• Participate in design reviews and contribute to clear, thorough design documentation
• Support silicon bring-up, block-level evaluation, characterization, and debugging
• Apply best practices for analog design, verification, and sign-off

Senior/Staff Analog IC Design Engineer

• Define microarchitecture for complex digital blocks and subsystems
• Actively contribute to RTL development for key components
• Drive design tradeoffs across performance, power, area (PPA), and testability
• Write, review, and integrate high-quality RTL
• Lead block- and chip-level integration, resolving interface and system issues
• Ensure RTL is optimized for synthesis, timing, and physical design
• Work on scan insertion, test architecture, and coverage closure
• Perform, review and debug logic equivalence checking (LEC) results between RTL and netlists
• Define and validate timing constraints (SDC) and complete timing closure
• Drive and implement timing and functional ECOs as needed
• Drive signoff readiness including lint, CDC/RDC, synthesis, LEC, and timing checks
• Ensure designs meet functional, timing, power, and test requirements
• Support silicon bring-up, debug, and root-cause analysis
• Work closely with verification, physical design, DFT, and firmware teams
• Align design decisions with verification plans and implementation

Principal Digital Design Engineer

Solutions Engineer

• Enable customer to design GPU/CPU SoC power solution with PowerLattice’s chiplet
• Assist customer’s PDN design optimization using PowerLattice’s design kit
• Gather customer feedback and translate insights into improvements for customer enablement and product development
• Assist customers through the full adoption lifecycle, from early modeling through physical design and system bring-up
• Maintain strict confidentiality and handle sensitive technical information with discretion
• Act as a primary technical point of contact for tier-one customers

Power Delivery Solution Architect

• Drive the implementation of complex SoC designs from netlist to tapeout.
• Develop and own chip-level and block-level floorplans, including macro placement and partitioning.
• Define and implement power distribution networks, including digital power grid creation.
• Integrate and ensure robust power connectivity for analog blocks and ESD structures.
• Optimize floorplan for performance, congestion, and power integrity.
• Perform and manage special routing for sensitive analog signals, ensuring signal integrity and isolation.
• Collaborate closely with analog designers on layout constraints, shielding, and noise mitigation.
• Ensure proper integration of analog macros within digital environments.
• Execute standard cell placement, optimization, and congestion management.
• Perform clock tree synthesis (CTS) and clock optimization.
• Drive global and detailed routing with focus on timing, SI, and manufacturability.
• Implement timing and functional ECOs to achieve design closure.
• Run and analyze physical verification flows including DRC, LVS, and antenna checks.
• Debug and resolve all layout violations to achieve clean signoff.
• Drive timing closure across all corners and modes.
• Collaborate with STA teams on setup/hold closure and constraint validation.
• Optimize design for PPA (power, performance, area) targets.

Senior/Staff Analog IC Design Engineer

Principal Digital Design Engineer

Power Delivery Solution Architect

Staff Physical Design Engineer