Advanced IC Packaging Engineer

Powerlattice Inc

Pioneering advanced IC packaging solutions integrating power delivery chiplets within substrates at a semiconductor startup. Defining architecture and leading innovations in AI compute technology.

Posted 7/2/2026full-timeChandler • Arizona • 🇺🇸 United StatesSeniorLead💰 $175,000 - $225,000 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in advanced IC packaging solutions, including power delivery chiplet integration and process optimization. Proficient in statistical analysis and DoE methodologies to enhance manufacturing processes and product reliability.

Highest-signal resume keywords

Advanced IC PackagingPower Delivery Chiplet IntegrationDesign of Experiments (DoE)Statistical AnalysisFailure Analysis

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Semiconductor PackagingProcess OptimizationReliability TestingSoldering ProcessesInterconnect ReliabilityChiplet IntegrationPackage-System Co-DesignRoot Cause IdentificationProduct QualificationAdvanced Packaging (2.5D/3D)

Soft Skills

Ability to Operate in AmbiguityDecision-MakingCollaboration

Certifications & Qualifications

Advanced Degree (MS/PhD) in Electrical Engineering, Materials Science, or Mechanical Engineering

Industry Keywords

HyperscalersOSATsTesting EcosystemsSupply Chain Ecosystems

Tech Stack

Tools & technologies

Assembly

About the role

Key responsibilities & impact

Responsible for the end-to-end development of advanced IC packaging solutions integrating power delivery chiplets into package substrates.
Architect and deliver first-of-its-kind land-side assembly and embedded chiplet integration within substrate cores.
Build packaging technologies from concept through high-volume manufacturing (HVM), including design, materials, process, test and reliability.
Establish and optimize Design of Experiments (DoE) frameworks to accelerate process development, yield learning, and performance optimization.
Develop statistical models and apply rigorous data analysis to drive design decisions, process control, and yield improvement.
Drive assembly process development, including novel flows for chiplet integration, substrate embedding, advanced interconnects and structure for reliability tests.
Partner directly with hyperscalers, ASIC, GPU, and xPU customers to integrate power delivery chiplets into their platforms.
Work closely with OSATs, testing, substrate vendors, and materials suppliers to build scalable, manufacturable solutions.

Requirements

What you’ll need

Advanced degree (MS/PhD preferred) in Electrical Engineering, Materials Science, Mechanical Engineering, or related field.
8+ years of experience in semiconductor packaging with deep expertise in advanced packaging (2.5D/3D, chiplets, substrate integration, test, reliability).
Proven experience taking packaging technologies from early concept to production including process and product qualification.
Strong background in power delivery, signal/power integrity, and package-system co-design.
Hands-on experience with DoE methodology, statistical analysis, and process optimization in a manufacturing or R&D environment.
Deep expertise in failure analysis, including root cause identification and corrective action across multiple domains.
Strong understanding of soldering processes, interconnect reliability, and assembly defect mechanisms.
Experience working with external manufacturing partners (OSATs), testing and supply chain ecosystems.
Ability to operate in ambiguity, move fast, and make high-quality technical decisions with limited data.

Benefits

Comp & perks

Stock option grant
Comprehensive benefits package including health, dental, vision, and 401(k)