NVIDIA

Full-stack Engineer

• use your design abilities, coding expertise, and creativity to deliver the best compute platform in the world
• craft elegant solutions to exciting problems
• shape the future direction of CUDA as you collaborate with your peers across NVIDIA
• evangelize, architect, and implement new features
• coordinate and drive development efforts across multiple teams
• help define forward-looking improvements to the CUDA APIs and programming model
• write effective, maintainable, and well-tested code
• develop code for multiple operating systems

Senior Systems Software Engineer, CUDA Driver

Engineer

• Join a team of experts working together to improve developer productivity for the NVIDIA driven software ecosystem.
• Develop and maintain continuous development systems through various software verticals spanning from end-users, through layers of open-source software, down to NVIDIA's math libraries, compilers, and drivers.
• This is a true software engineering role.
• The team creates tools and infrastructure, debugs issues as they arise, and fixes problems across the entire stack.
• Together, we stabilize and deliver the entire NVIDIA software stack to the world at global scale.
• This is a development-focused role that drives software quality and reliability without on-call duties.

Senior Life Cycle Engineer, PyTorch – Deep Learning

Program Manager

• Drive reporting and visibility of sales activities, including pipeline development and progression from ISVs, OEMs, and channel partners in SFDC.
• Gather and manage sales enablement assets from NVIDIA software solution partners for distribution to reseller channels, inspiring the NVIDIA ecosystem to invest in joint demand-generation activities.
• Activate sales motions by orchestrating sales programs and activities, coordinating scalable partner sales trainings, sales strategies, and demand-generation programs.
• Coordinate engagement with NVIDIA’s worldwide field teams and key account managers to ensure partner sales success.

Go-To-Market Program Manager, Physical AI

Architect

• Develop ECNs addressing requirements for new capabilities and steer them through industry standards organizations such as PCIe, CXL, and UCIe
• Drive internal architecture of our designs for adoption of features and capabilities in industry specifications
• Engage with customers and partner companies to develop interconnect strategies and understand requirements for our future AI and graphics systems
• Work across architecture, software, hardware design, and verification teams to align functionality, compliance, and roadmaps
• Conduct deep-dive analysis into PCIe performance, identifying and resolving bottlenecks, improving data throughput, and analyzing complex memory ordering requirements to ensure data consistency and efficiency

Senior I/O Specifications Architect

Systems Engineer

• Building and maintaining infrastructure from first principles needed to deliver TensorRT LLM
• Maintain CI/CD pipelines to automate the build, test, and deployment process and build improvements on the bottlenecks.
• Managing tools and enabling automations for redundant manual workflows via Github Actions, Gitlab, Terraform, etc
• Enable performing scans and handling of security CVEs for infrastructure components
• Improve the modularity of our build systems using CMake
• Use AI to help build automated triaging workflows
• Extensive collaboration with cross-functional teams to integrate pipelines from deep learning frameworks and components is essential to ensuring seamless deployment and inference of deep learning models on our platform.

Senior Infrastructure and Build Systems Engineer

• Participate in every stage of development of a GPU
• Thrive at the interface between software drivers and the GPU simulation
• Coordinate with GPU architects to enable functional and performance testing for the next architecture
• Work closely with SW teams to help them deliver production-ready drivers when silicon goes to market
• Improve the daily workflows of leading chip modelers and designers around the globe to help produce the next greatest generation of GPUs

System Software Engineer, GPU Development Tools

Cloud Engineer

• Collaborate with data center network/security architects and vendor partners to build the next generation of streaming technology for cloud-based ultra-low-latency applications.
• Research, develop, and innovate network routing and QoS algorithms for secure ultra-low streaming and improve user experience.
• Collaborate with our partners to build the next generation of networking gear optimized for low-latency streaming.
• Use data analytics to measure user experience and develop features to grow our satisfied user base.
• Define, implement, and improve industry-leading KPIs for networking, streaming quality, latency, and stutter.
• Generate networking models that simulate various real-life end-user networks.

Senior Systems Software Engineer – Cloud Networking

• Design and build learned evaluation pipelines that assess driving behavior using LLMs, VLMs, and multimodal models
• Develop agentic workflows that chain model inference, retrieval, and structured reasoning to evaluate complex driving scenarios
• Define evaluation-of-evaluation methodology — how do we know our learned evaluators are correct?
• Build golden-set frameworks and calibration loops for learned metrics
• Partner with AML (Alpamayo Logos) teams on model-specific eval needs (e.g., COT prediction quality, AML regression coverage)
• Instrument evaluation systems with robust experiment tracking, A/B comparison tooling, and model versioning
• Contribute to the team's transition from rule-based to learned evaluation: identify metrics and analyzers that are candidates for ML replacement and build the alternatives

Senior ML Evaluation Engineer – Autonomous Vehicles

• Understand the design & implementation with focus on Memory Management unit
• Define the verification scope
• Develop the verification infrastructure (Testbenches, BFMs, Checkers, Monitors)
• Implement test/coverage plans
• Verify the correctness of the design
• Collaborate with architects, designers, software engineers across sites
• Plan and work on strategic direction of the methodology for the testbench

ASIC Verification Engineer

Security Engineer

• Be involved in offensive security researcher on a wide range of products.
• Assist with defining and making sure software development processes meet security and coding standards.
• Perform security threat modeling for NVIDIA Networking products.
• Design and make security architecture recommendations to satisfy security guidelines and requirements.
• Mentor teams and developers, promoting guidelines on the best security practices.
• Be a technical focal point across multiple development teams and provide hands-on security engineering expertise.

Software Security Researcher

Mechanical Engineer

• Be responsible for understanding specific protocol concepts and features
• Make architectural trade-offs based on feature/performance/power requirements
• Analyze system implications, develop micro-architecture
• Implement RTL, drive the verification, close timing, and support silicon validation
• Own micro-architecture and RTL development of design modules
• Micro-architect features to meet performance, power and area requirements
• Work with HW architects to define critical features
• Collaborate with verification teams to verify correctness

Senior ASIC Design Engineer, High Speed IO

• Develop UVM-based verification test benches and methodologies for unit level
• Write verification components and API's for cluster and system level test benches
• Verify dedicated CPU sub-systems targeted for Audio processing, Functional Safety, RAS, BOOT and power management
• Architect the testbenches and craft verification environment using SV, UVM and C/C++ methodology
• Define test plans, tests and verification infrastructure for clusters and systems
• Build efficient and reusable bus functional models, monitors, checkers, scoreboards, API's and encapsulated components
• Implement functional coverage and own unit, cluster and SOC level verification closure
• Work with architects, designers, FPGA, and post-silicon teams to ensure that your unit is robust and feed back and bug escapes driven improvements to your setup

Senior Verification Engineer – Audio and Auxiliary CPU Sub-Systems

• Develop UVM-based verification test benches and methodologies.
• Verify complex rapid data transfer IO IPs and sub-systems such as USB, UFS, MPHY, Ethernet, and MACSEC.
• Architect the testbenches and craft verification environment using SV and UVM methodology.
• Define test plans, tests and verification infrastructure for modules, clusters and systems.
• Build efficient and reusable bus functional models, monitors, checkers, and scoreboards.
• Implement functional coverage and coordinate the verification closure process for the unit.
• Work with architects, designers, FPGA, and post-silicon teams to ensure that your unit is robust.

Senior Verification Engineer – HSIO Unit Level

• Define the Network Adapter chip architecture end to end from the market requirements through design and all product life cycles (post/pre-silicon, on deployments).
• Work with related industry standards & customers on deploying your tech.
• Collaborate with teams across teams (physical design, logic design, system software, firmware, applications)
• Work on proof of concepts and advance development projects.
• Perform research and analysis for current and future architectures.
• Simulate complex architectural features.
• Craft product design specifications.
• Serve as a focal point within the organization and distribute the knowledge that you acquire.

Senior Chip Architect

AI Engineer

• Research and develop techniques to GPU accelerate workloads in deep learning, machine learning or other AI domains.
• Work directly with other technical experts in their fields (industry and academia) to perform in-depth analysis and optimization of complex AI and HPC algorithms.
• Publish and/or present discovered optimization techniques in developer blogs or relevant conferences.
• Influence the design of next-generation hardware architectures, software, and programming models in collaboration with research, hardware, system software, libraries, and tools teams at NVIDIA.