NVIDIA

Marketing

• Developing co-marketing plans with our ISV that generate awareness, thought leadership, and demand for our Enterprise platforms.
• Enabling and supporting the execution of such marketing plans with partners.
• Working closely with partners to identify accelerated computing and AI marketing collaboration opportunities.
• Supervising marketing execution by implementing accountability and responsiveness to improve return on investment.
• Collaborate with Product, Sales, and Business Development teams to build increasingly effective campaigns that support the NVIDIA product roadmap.
• Building a trusted and valued relationship with your partner contacts.

Senior Partner Marketing Manager – ISV

Artificial Intelligence

• Analyzing deep learning networks and developing compiler optimization algorithms
• Collaborating with members of the deep learning software framework teams
• Defining public APIs, performance optimizations and analysis
• Crafting and implementing compiler techniques for AI workloads

Senior Compiler Engineer, AI Inference Performance

• Analyzing deep learning networks and developing compiler optimization algorithms
• Collaborating with members of the deep learning software framework teams and the GPU architecture teams to accelerate the next generation of deep learning software
• Defining public APIs, performance optimizations and analysis, crafting and implementing compiler techniques for AI workloads and future NVIDIA GPUs

Senior Compiler Engineer, AI Inference Platforms

Backend Engineer

• Develop creative architectures and system software implementations to enable scalable multi-GPU platforms
• Understand and analyze the interplay between operating systems, CPU and GPU architectures, and efficient algorithm designs
• Collaborate with diverse teams across the company, spanning software, research, hardware engineering, and product groups
• Publish original research and speak at conferences and events

Research Scientist, Platform Architecture and System Software

Security Analyst

• Lead Incident Response efforts for corporate, cloud, and product environments, including investigation, containment, eradication, and recovery.
• Perform threat hunting across endpoints, networks, and cloud workloads to proactively identify indicators of compromise, emerging threats, and control gaps.
• Conduct cloud incident response for AWS, Azure, and GCP, and other cloud environments including Kubernetes and containerized workloads, performing log analysis, identity compromise investigations, and workload forensics.
• Drive product security incident response, collaborating with engineering teams to analyze potential exposure to vulnerabilities, exploits, and security flaws in NVIDIA products.
• Perform digital forensics and malware analysis to support investigations and root cause analysis.
• Develop and optimize security orchestration and automation playbooks in partnership with Security Engineering to accelerate detection and response.
• Build and refine detections and defense strategies based on threat models and attacker behaviors across cloud, identity, endpoint, and product telemetry, using frameworks such as MITRE ATT&CK to map adversary tactics and enhance detection coverage.
• Provide guidance to engineering and business teams on secure design and incident handling standards and contribute to security policies, standards, and metrics to continuously improve NVIDIA’s security posture.

Cyber Security Analyst

Engineer

• Own and drive the definition, planning, and execution of verification strategies for sophisticated CPU designs.
• Apply brand new verification methodologies and techniques to improve efficiency and ensure continuous improvement in CPU verification.
• Collaborate closely with global architecture, build, and verification teams to complete and prioritize tasks.
• Partner with build and architecture teams to define the scope of verification for high-quality product delivery.
• Develop and maintain comprehensive stimulus, testbench, and coverage strategies to ensure continuous progress toward tape-out through defined metrics.
• Mentor and guide a team of verification engineers, encouraging an environment of growth and learning.
• Demonstrate agility in balancing multiple tasks and projects simultaneously.

Senior Verification Engineer – CPU

Full-stack Engineer

• Building and maintaining a scalable, distributed platform for automated security and quality scanning that integrates seamlessly with CI/CD pipelines across a range of services and environments.
• Designing and developing foundational libraries and APIs that standardize how security evidence is generated, formatted, and ingested—enabling internal and external tools to integrate smoothly with our systems.
• Defining and evolving evidence schemas and data models that enable accurate, consistent, and scalable insights into application security and software composition.
• Building robust services—primarily in Python and Go—that operate reliably in distributed, cloud-native environments, leveraging Docker, Kubernetes, and infrastructure-as-code practices.
• Collaborating closely with developers and platform teams to understand workflows and problems, delivering solutions that enhance developer productivity, software reliability, and security posture.
• Driving cross-functional initiatives that influence how scanning and quality insights are integrated across the SDLC, with visibility and impact at the organizational level.

Senior Software Engineer – Scanner Automation

• Take a comprehensive view of the ASIC development lifecycle, identifying cross-stage bottlenecks and opportunities where automation and AI can improve predictability, convergence, and turnaround time.
• Identify, curate, and leverage real-time data to enable effective AI models and analytics, working with infrastructure teams to ensure scalable and secure data pipelines.
• Establish quantitative metrics to measure efficiency, quality, and cycle-time improvements; use data-driven insights to guide methodology decisions and prioritize investments.
• Serve as a technical catalyst within both the team and the wider company by sharing best practices, publishing internal guidelines, and mentoring engineers on emerging AI-enabled development techniques.
• Track advances in AI, EDA, and hardware design research, evaluating their applicability and guiding strategic bets that align with long-term product and technology roadmaps.

Senior ASIC Methodology Engineer

Human Resources

• Lead HR operational processes for the Federal Public Sector Entity
• Establish and maintain compliant, scalable workflows and controls
• Support audit readiness and documentation standards
• Manage end-to-end onboarding aligned with regulatory, contractual, and security requirements
• Oversee employee lifecycle events including transfers, role changes, and status updates
• Ensure accurate documentation and compliance tracking
• Own and maintain the Federal Public Sector Employee Handbook
• Partner with Legal, Security, and Compliance on policy updates and version control
• Provide guidance on policy interpretation and application
• Lead compliant separation processes and required documentation
• Coordinate cross-functional activities for access removal and final pay processing
• Identify process improvements that strengthen compliance and reduce risk

HR Lead – Public Sector

• Drive upstream-first engineering in vLLM/SGLang: author and land PRs or equivalent experience, engage in development discussions, help compose roadmaps, and build durable maintainer relationships.
• Build and implement inference-runtime features that improve efficiency, latency, and tail behavior: request scheduling, batching policies, KV-cache management (paging/sharding), memory planning, and streaming.
• Optimize core hot paths across the stack—from Python orchestration down to C++/CUDA kernels—using profiling and measurement to guide decisions.
• Improve multi-GPU and multi-node inference: communication patterns, parallelism strategies (tensor/sequence/pipeline), and system-level scaling/efficiency.
• Strengthen correctness, robustness, and operability: determinism where needed, graceful degradation, backpressure, observability hooks, and performance regression testing.
• Collaborate across NVIDIA to integrate upstream advances with production needs (deployment patterns, compatibility, security posture) while keeping changes broadly adoptable by the community.
• Mentor senior engineers, raise the technical bar through build reviews, and establish guidelines for performance engineering and upstream contribution workflows.

Principal Software Engineer – AI Inference

Mechanical Engineer

• Improving Voltage/Frequency/Power/Thermal Envelope of Nvidia Products
• Architect new Chip/System features to improve testable power, V/F, speed grades, temp, or test time
• Define the methodology for how manufacturing tests, SRAM, binning, or package technology constraints should be incorporated into product V/F curves, vmin, and TGP.

Senior System Manufacturing Co-Design Engineer

DevOps Engineer

• Running commissioning and provisioning for GPU systems
• Running the firmware versions of equipment and components, and communicating the supported versions across the organization
• Through Day-2 operations, keeping tight SLOs around efficiency, performance, and availability
• Monitoring the hardware state of the cluster, finding bottlenecks and hot spots, and helping users attain peak performance constantly
• Triaging the HW break-fix issues and making constant improvements using open-source break-fix solutions
• Collaborate with programming and technical divisions to define and implement repeatable procedures
• Develop and implement operations strategy & processes, maintaining consistency with SLAs across critically important infrastructure
• Develop and apply procedures for minimal downtime and quality controls to strive to achieve continuous uptime
• Feeding requirements to software and hardware teams
• Creation of documentation that the ecosystem can use to run its own AI Data Centers

Senior Site Reliability Engineer, AI Factory

• Working on backend and frontend design and development of web applications.
• Collecting requirements and provide consultation to end users about their needs and use cases.
• Analyzing performance bottlenecks.
• Supporting and maintaining large scale data platform with high QoS.
• Building infrastructure and microservices for various big-data scenarios.

Senior Full-stack Web Applications Software Engineer

Machine Learning Engineer

• Build, develop, and maintain high-performance runtime and compiler components, focusing on end-to-end inference optimization.
• Define and implement mappings of large-scale inference workloads onto NVIDIA’s systems.
• Extend and integrate with NVIDIA’s SW ecosystem, contributing to libraries, tooling, and interfaces that enable seamless deployment of models across platforms.
• Benchmark, profile, and monitor key performance and efficiency metrics to ensure the compiler generates efficient mappings of neural network graphs to our inference hardware.
• Collaborate closely with hardware architects and design teams to feedback software observations, influence future architectures, and codesign features that unlock new performance and efficiency points.
• Prototype and evaluate new compilation and runtime techniques, including graph transformations, scheduling strategies, and memory/layout optimizations tailored to spatial processors.
• Publish and present technical work on novel compilation approaches for inference and related spatial accelerators at top tier ML, compiler, and computer architecture venues.

Senior Machine Learning Engineer – Applications, Compilers

• Develop ground-breaking methodologies and innovations to create flawless experience in chip design development
• Utilize, develop and Assimilate AI-based tools and flows
• Collaborate with chip design stakeholders and peers across the teams to understand existing problems and form the best solutions and methodologies
• Get in touch with EDA vendors to learn about cutting-edge tools/technology and apply them into our development process
• Develop training sessions and guide designers with best design practices
• Develop shared design code and solutions to be widely used by the chip design team