Senior Mechanical Engineer
Fervo Energy
Senior ASIC Design Engineer – Clocks IP
NVIDIA
full-time
Posted on:
Location Type: Hybrid
Location: Santa Clara • California, Texas • 🇺🇸 United States
Visit company websiteSalary
💰 $136,000 - $264,500 per year
Job Level
Senior
Tech Stack
Python
About the role
- Architect the clock domain to satisfy functional, physical and testing design requirements
- Engage with multiple teams to design GPU or CPU clocks meeting architectural, design, and physical constraints
- Improve Power, Performance, and Area (PPA) by evaluating trade-offs across DFx, Physical Implementation, Power Optimization and timing closure
- Innovate and implement new clocking topologies in RTL
- Collaborate with Physical design and timing teams to evaluate clocking concerns and develop solutions for high speed clocking
- Deliver clock RTL information to GPU, CPU and SoC verification, timing and DFT teams
- Participate in end-to-end ASIC execution from micro-architecture, design implementation, sign-off checks to silicon bringup
- Work with front design, floor-planning, back-end, software programming model, and silicon solution teams to triage silicon or programming bugs in the lab
Requirements
- BS in Electrical Engineering or equivalent experience (MS preferred)
- 3+ years of relevant work experience
- Deep understanding of logic optimization techniques and PPA trade-offs
- Excellent interpersonal skills and ability to collaborate with multiple teams
- Experience in RTL design (Verilog), verification and logic synthesis
- Strong coding skills in python or other industry-standard scripting languages
- Understanding of sub-micron silicon issues like noise, cross-talk, and OCV effects is a plus
- Implementing on-chip clocking networks is a bonus
- Experience with clocks controller and clocks logic design (way to stand out)
- Understanding of system level artifacts like power and noise (way to stand out)
- Experience with scalable designs and architecture (way to stand out)
- Hands-on silicon debug is a plus
Benefits
- Competitive salary
- Eligible for equity
- Generous benefits package
- Hybrid work arrangement
Applicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard skills
RTL designVeriloglogic optimization techniquesPPA trade-offspythonscripting languagesclocking networksclocks controller designsilicon debugscalable designs
Soft skills
interpersonal skillscollaboration
Certifications
BS in Electrical EngineeringMS in Electrical Engineering
