Senior Design Engineer
GoFundMe.org
JavaScriptReactTypeScript
Senior ASIC Design Engineer – Clocks IP
NVIDIA
full-time
Posted on:
Location Type: Hybrid
Location: Santa Clara • California, Texas • 🇺🇸 United States
Visit company websiteSalary
💰 $136,000 - $264,500 per year
Job Level
Senior
Tech Stack
Python
About the role
- Architecting the clock domain to satisfy functional, physical and testing design requirements
- Engage with multiple teams and design the GPU or CPU clocks to satisfy architectural, design and physical constraints
- Improve Power, Performance, and Area (PPA) by evaluating trade-offs across DFx, physical implementation, power optimization and timing closure
- Innovate and implement new clocking topologies in RTL
- Collaborate with physical design and timing teams to evaluate clocking concerns and develop high-speed clocking solutions
- Deliver clock RTL information to GPU, CPU and SoC verification, timing and DFT teams
- Participate in end-to-end ASIC execution: micro-architecture, design implementation, fixes, sign-off checks and silicon bringup
Requirements
- BS in Electrical Engineering or equivalent experience (MS preferred)
- 3+ years of relevant work experience
- Deep understanding of logic optimization techniques and PPA trade-offs
- Excellent interpersonal skills and ability to collaborate with multiple teams
- Experience in RTL design (Verilog), verification and logic synthesis
- Strong coding skills in python or other industry-standard scripting languages
- Understanding of sub-micron silicon issues like noise, cross-talk, and OCV effects (plus)
- Implementing on-chip clocking networks (bonus)
- Experience with clocks controller and clocks logic design (ways to stand out)
- Understanding of system-level artifacts like power and noise (ways to stand out)
- Experience with scalable designs and architecture (ways to stand out)
- Hands-on silicon debug (plus)
Benefits
- Competitive salaries
- Generous benefits package
- Eligible for equity
- Hybrid work arrangement (#LI-Hybrid)
Applicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard skills
RTL designVeriloglogic synthesispower optimizationtiming closureclocking topologieslogic optimization techniquessilicon debugscripting languagesscalable designs
Soft skills
interpersonal skillscollaborationcommunication
Certifications
BS in Electrical EngineeringMS in Electrical Engineering
