Staff Hardware Architect
Serve Robotics
Senior Engineer, Physical Design
Marvell Technology
full-time
Posted on:
Origin: • 🇮🇱 Israel
Visit company websiteJob Level
Senior
About the role
- Work on both the physical design of complex chips and the methodology for efficient, robust design processes.
- Work hands-on to triage workflows, running RTL through synthesis and place and route (PnR) tools to create the physical view of the chip.
- Analyze performance by running timing analysis and verify power grid by performing EMIR analysis.
- Review completed runs for errors and create optimizations from successful runs; perform sign-off checks to verify database readiness.
- Collaborate with a global team on next-generation, high-performance processor chips targeted at server, 5G/6G, and networking applications.
Requirements
- Bachelor’s, Master’s, or PhD degree in Electrical Engineering, Computer Engineering, or a related field.
- 3+ years of experience in physical design with a focus on block-level PNR for advanced CMOS process nodes (e.g., 7nm, 5nm, or below).
- Working experience with industry-standard EDA tools for physical design, including Cadence Genus and Innovus, and Synopsys IC Compiler and Fusion Compiler.
- Working knowledge of static timing analysis tools such as Tempus or PrimeTime and EM/IR-Drop/Crosstalk analysis tools like Voltus or PrimeRail is advantageous.
- Working knowledge of physical verification and formal verification tools (e.g., Calibre, LEC, Formality) is advantageous.
- Enjoy learning by doing the work and having access to guides and a mentor.
- Be willing to raise your hand and volunteer for learning opportunities you may not have experienced before.
- Applicants must be eligible to access export-controlled information; non-U.S. applicants may be subject to export license review.
