Intel Corporation

Financial Planning and Analysis

• Analyze revenue, pricing, and financial data to help teams make better business decisions
• Evaluate customer pricing and mix trends to support revenue planning and margin evaluation
• Execute and organize major finance processes across finance and operations, including forecast and close quarterly cycles
• Partner on AI-enabled solutions that reduce manual work and improve recurring finance processes
• Collaborate cross-functionally with finance and operations teams to ensure process efficiency and accuracy
• Drive automation initiatives and leverage AI technologies to enhance modeling capabilities and generate actionable business insights
• Maintain process organization to ensure timely completion of all financial cycles and deliverables
• Identify opportunities for process improvement and enhanced analytical capabilities

Revenue Financial Analyst

• Support execution of the LRP and financial planning processes by maintaining high-quality data inputs
• Perform data validations and reconciliations
• Build and enhance control checks
• Analyze disconnects across source data and assumptions
• Develop reports, trackers, and performance metrics
• Collaborate with Finance, Operations, and cross-functional stakeholders
• Contribute to automation and continuous improvement initiatives

Central Financial Analyst

Hardware Engineer

• Design, implement, and verify hardware design tools, flows, and methodologies for advanced technology nodes
• Develop unique hardware designs and integrate components into hierarchical systems for end-to-end EDA tool testing
• Analyze and optimize methodologies for improved power, performance, area, and efficiency in hardware development
• Build platforms, databases, scripts, and tool flows to enhance design automation capabilities
• Test and analyze engineering design automation tools to ensure reliability, functionality, and quality
• Develop and refine tools to support digital design, verification, structural and physical layout, full-chip integration, power optimization, clocking, and timing methodologies
• Work collaboratively with EDA vendors to define, test, and adopt next-generation design tools

Senior EDA Tools Hardware Engineer

Mechanical Engineer

• Define microarchitecture and implement RTL for SoC blocks
• Collaborate with IP providers to integrate IPs into the SoC
• Collaborate with verification and firmware teams to meet functional and performance goals
• Own design quality including clock/reset/power domain crossings and timing constraints
• Collaborate with physical design teams to meet timing/area/power goals
• Drive high-quality design handoffs to partner teams (verification, physical design, firmware, packaging)

Senior AI SoC Design Engineer

• Define microarchitecture and implement RTL for SoC blocks
• Collaborate with IP providers to integrate IPs into the SoC
• Collaborate with verification and firmware teams to meet functional and performance goals
• Own design quality including clock/reset/power domain crossings and timing constraints
• Collaborate with physical design teams to meet timing/area/power goals

Designer

• Perform functional verification of mixed signal logic components, including analog behavioral modeling, to ensure design specifications are met.
• Develop IP verification plans, test benches, and verification environments to ensure comprehensive coverage of mixed signal microarchitecture specifications.
• Execute detailed verification plans, define and run system simulation models, analyze power and timing, and uncover bugs to optimize design functionality.
• Debug issues in the presilicon environment through replication, root cause analysis, and implementation of corrective measures to resolve failing tests.
• Collaborate with digital and analog architects, RTL developers, and physical design teams to enhance the verification of complex architectural and microarchitectural features.
• Drive technical reviews of test plans and proofs with design and architecture teams, documenting all processes and findings.
• Maintain and continually improve functional verification infrastructure, methodologies, and tools to align with evolving industry standards.

Mixed Signal Design Verification Engineer

Full-stack Engineer

• Build and scale production-grade data infrastructure for agentic AI systems.
• Engineer resilient platforms for long-running agent workflows and multi-agent coordination.
• Deliver data pipelines and integrations that connect agents to enterprise data.
• Productionize graph-based orchestration for planner-executor-validator patterns.
• Implement explicit state and control flows.
• Enable robust agent-tool integration across APIs, services, data systems.
• Support multi-agent collaboration patterns.
• Design and maintain data pipelines connecting distributed enterprise data.
• Build and operate event streaming, API management infrastructure.
• Define and track SLIs/SLOs for task completion reliability.
• Implement CI/CD practices tailored for agent deployments.
• Optimize compute, storage, and inference paths for sustained agent throughput.
• Implement full-stack observability for agent runs.

AI Software Development Engineer

Sales Operations Manager

• Own customer-level business performance, including unit and revenue forecasting aligned to Plan/POR commitments
• Drive forecast accuracy through data analysis, market insights, and cross-functional collaboration
• Maximize revenue through supply allocation, inventory management, and pricing strategy execution
• Lead operational execution across supply chain programs, ensuring alignment with customer and regional goals
• Partner with Customer Business Analysts, Rebate Analysts, and Customer Operations to execute account strategy
• Identify and implement operational efficiencies to improve processes and business outcomes
• Proactively escalate critical customer issues to senior regional leadership and drive resolution
• Influence decision-making through data-driven insights, clear communication, and stakeholder alignment
• Coach and support Customer Business Analysts in managing account performance and operational execution

Temporary Sales Operations Analyst

Security Engineer

• Develop and support security solutions that integrate and interface with customers/business units.
• Assist with ongoing capability development on Intel's big bet platforms (Kafka, Splunk, etc.) including future integrations/development.
• Work closely with software development engineers, system engineers, and other information security teams in supporting information security projects and initiatives.
• Support and work in an Agile and DevOps team focused on security analytics and solution development.
• Deal with initial ambiguity and seek to provide clarity around target systems and objectives.
• Verify efficacy of security controls implemented on a variety of Intel enterprise systems, infrastructure, and applications.
• Develop quality reporting documentation, tailoring the relative detail of the content to the audience.
• Recommend remediation actions to discovered security vulnerabilities and weaknesses.
• Be a team player within the functional team, and also across other Intel teams and stakeholders.
• Support vulnerability assessments of AI systems by running scans, documenting findings, and helping track remediation of identified issues in models and datasets.
• Participate in secure coding and development practices for AI-enabled applications, ensuring adherence to established security standards and code review processes.
• Collaborate with cross-functional teams to understand AI workflows and identify potential security gaps.
• Help develop AI agents to respond to AI attackers.

Information Security Engineer

• Lead pre-silicon functional verification of complex CPU and SoC logic to ensure compliance with architectural specifications
• Develop and execute verification plans, testbenches, and SystemVerilog/UVM environments
• Define, run, and analyze system-level simulations to uncover issues
• Debug and root-cause complex RTL and integration issues, driving resolution with design teams
• Collaborate cross-functionally to improve design quality and verification effectiveness
• Maintain and enhance verification infrastructure and methodologies
• Document verification strategies, results, and findings
• Lead technical discussions and design reviews.

Senior CPU Design Verification Engineer

Accounting Manager

• Serve as a technical accounting expert for Revenue and Rebate accounting under ASC 606, providing authoritative guidance on complex and non routine transactions, including long term agreements, deposits, rebates, price concessions, and contract modifications.
• Interpret U.S. GAAP and develop, maintain, and review accounting policy positions, whitepapers, and technical memos to support revenue and rebate conclusions.
• Review customer contracts, and amendments to identify accounting implications and areas of judgment under ASC 606.
• Act as a trusted advisor to Sales, Finance, Legal, and Product and Foundry teams during deal structuring and negotiation, ensuring accounting considerations are understood and appropriately reflected.
• Provide judgment on rebate arrangements, pricing adjustments, funding arrangements, and other forms of variable consideration to determine appropriate revenue versus contra expense treatment.
• Partner with Systems, Data, and Technology teams to translate accounting policy and judgment requirements into scalable enablement solutions.
• Support management inquiries, executive reviews, and internal control considerations related to revenue recognition policy and application.

Revenue and Rebate Accounting Manager

Engineer

• Drive technology development initiatives that enable both high-volume manufacturing and future technology advancement
• Provide comprehensive process integration and equipment solutions
• Conduct feasibility studies to meet target device specifications
• Lead design and development of sophisticated manufacturing processes, including material selection, parameter optimization, equipment metrology, and system design
• Optimize production output for existing products
• Partner with key equipment and materials suppliers to develop enabling technology elements
• Perform process technology feasibility studies using theoretical simulations and practical engineering methods
• Stay current with industrial process and material manufacturing trends
• Develop insights into future Intel process technology needs
• Partner with vendor ecosystem to build cost-sensitive technology roadmaps
• Influence and drive technical direction across Intel and the broader industry
• Develop and mentor technical leaders within the organization

Senior Process Engineer – Dry Etch

Administration

• Provides senior administrative support and program coordination to the Chief Counsel, International, and the leadership team across EMEA, APJ and China
• Serve as a proactive administrative partner to the Chief Counsel, International (based in UK) and her globally located leadership team
• Own calendar and meeting logistics by triaging and prioritizing inbound requests, managing competing demands and protecting leadership time
• Independently manage frequent international travel and meeting needs using appropriate judgement and technology
• Prepare agendas and materials, capture actions, and drive follow-up to support execution and accountability
• Own and simplify budget tracking, reporting cadence/accuracy and law firm invoice management
• Own preparation of operational dashboards, using matter management tools to pull relevant data
• Identify trends, risks, and variances; propose corrective actions and streamline reporting
• Track delivery of team priorities and education programs, ensuring clarity of ownership and progress
• Be an active member of internal and external admin and program coordinator communities

Senior Administrator – Program Coordinator

• Operate and sustain manufacturing and Foundry network services to ensure high availability and operational stability.
• Deploy, configure, and support network infrastructure, primarily Cisco‑based platforms, in production manufacturing environments.
• Monitor network performance and capacity, identify operational risks, and support timely remediation to prevent factory impact.
• Collaborate effectively with cross‑functional global teams to deliver operational outcomes on schedule.
• Respond to network incidents, participate in structured troubleshooting, and support rapid service restoration to minimize manufacturing downtime.
• Participate in 24x7 on‑call rotations and operational escalations for factory‑impacting events.
• Execute network changes following established manufacturing change management and operational readiness processes.
• Support capacity and feasibility assessments under direction from senior engineers to enable safe factory growth.
• Support deployments of new capabilities, through collaboration with network engineering.

IT Network Operation Engineer

• Involving in the training, design and development of next generation SOC/CPU for wide range of Intel products
• Creates mask layouts of integrated circuits for a given specification
• Runs complete set of design verification tools for process design rules, electron migration, voltage drop (IR), ESD, and other reliability checks
• Creates accurate designs that meet project needs
• Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues
• Designs and analyzes floorplans, power grid, and bumps
• Troubleshoots a wide variety of issues up to and including layouts and tool/flow/methodology used in layout design

Revenue Financial Analyst

Central Financial Analyst

Senior EDA Tools Hardware Engineer

Senior AI SoC Design Engineer

Senior AI SoC Design Engineer

Mixed Signal Design Verification Engineer

AI Software Development Engineer

Temporary Sales Operations Analyst

Information Security Engineer

Senior CPU Design Verification Engineer

Revenue and Rebate Accounting Manager

Senior Process Engineer – Dry Etch

Senior Administrator – Program Coordinator

IT Network Operation Engineer

CPU-SoC Mask Layout Designer