Senior EDA Tools Software Engineer

Intel Corporation

Senior Software Engineer developing automation tools for Intel's Silicon Chassis team. Leading architecture and implementation of new tooling and collaborating with cross-functional teams.

Posted 7/14/2026full-timeRemote • 🇮🇳 IndiaSeniorWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in architecting and implementing automation tools for SoC programs, with a strong focus on scalability, maintainability, and extensibility. Proficient in digital design concepts and capable of leading cross-functional teams to deliver high-quality outputs.

Highest-signal resume keywords

Python ProficiencyDigital SoC Design ConceptsCAD/EDA Tooling ExperienceVersion Control (Git)Network-on-Chip (NoC) Architectures

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Chassis Automation Tool DevelopmentRTL GenerationRDL GenerationVerification Collateral CreationTiming AnalysisIntegration ArtifactsStructured Schema Design (JSON, YAML)SystemVerilog KnowledgeCode Generation FrameworksGraph-Based Algorithms

Soft Skills

Excellent CommunicationProblem-SolvingOrganizational SkillsMentoringCollaboration

Tools & Technologies

EDA ToolsCI/CD PracticesGUI DevelopmentUnit/Integration TestingTEMPLATING Systems

Industry Keywords

Semiconductor DevelopmentRTL DesignVerificationIP PackagingIP-XACT Standards

Tech Stack

Tools & technologies

Python

About the role

Key responsibilities & impact

Architect, design, and implement a new chassis automation tool to meet requirements across multiple SoC programs, ensuring scalability, maintainability, and extensibility.
Analyze chassis and interconnect architecture specifications, along with high-level SoC requirements, and build tooling and infrastructure to translate these requirements into generated outputs such as RTL, RDL, verification collateral, timing, and integration artifacts.
Develop automation flows that convert architectural intent into concrete implementations, including topology generation, parameter derivation, register definitions, and associated collateral.
Integrate with frontend and backend tool flows to enable robust validation and quality checks across generated artifacts (e.g., RTL, Verilog, SDC, RDL), ensuring correctness and consistency.
Enable Power, Performance, and Area (PPA) optimization loops by building automation and analysis capabilities that evaluate design trade-offs and guide configuration decisions.
Work closely with architecture, RTL design, verification, and SoC integration teams to ensure the tool accurately captures requirements and produces outputs that meet downstream expectations.
Participate in and contribute to technical reviews with cross-functional stakeholders, incorporating feedback to improve tool capabilities, usability, and quality.
Drive end-to-end execution from initial concepts and specifications through development, deployment, and ongoing maintenance of the automation framework.
Lead delivery of the tool and associated outputs to multiple internal customers, balancing competing requirements, schedules, and priorities while maintaining high quality.
Collaborate across organizational boundaries and contribute beyond immediate role scope when needed to unblock execution and ensure overall program success.
Mentor and guide engineers, helping establish best practices in software design, testing, and maintainability, and elevating overall team effectiveness.

Requirements

What you’ll need

Bachelor's or Master's degree in Electrical Engineering, Computer Science, or a related field, with 9+ years of experience in CAD/EDA tooling, design automation, or semiconductor development.
Strong proficiency in Python or similar language, with proven experience of building scalable, maintainable software systems and frameworks rather than one-off scripts.
Solid understanding of digital SoC design concepts, including RTL hierarchy, synthesis flows, and parameterized IP design.
Experience designing and validating structured schemas using formats such as JSON or YAML.
Working knowledge of SystemVerilog to understand and validate generated design outputs.
Experience with templating systems or code generation frameworks used for structured RTL or collateral generation.
Strong software engineering fundamentals including version control (Git), code reviews, unit/integration testing, and CI/CD practices.
Preferred: Experience with Network-on-Chip (NoC) architectures or high-performance interconnect protocols such as AXI, CHI, PCIe, UCIe, or similar.
Familiarity with IP packaging, configuration, and integration methodologies, including standards such as IP-XACT.
Exposure to industry EDA tools and design flows.
Knowledge of graph-based algorithms or data structures relevant to topology generation, connectivity modeling, or routing problems.
Prior experience working in a semiconductor product development environment, such as CAD, RTL design, or verification.
Experience in GUI development
Excellent communication, problem-solving, and organizational skills, with a track record of delivering high-quality solutions on schedule.

Benefits

Comp & perks

Health insurance
401(k) matching
Flexible work hours
Paid time off
Remote work options