SoC Physical Design Lead
Intel Corporation
Senior DFT Engineer
Intel Corporation
full-time
Posted on:
Location Type: Hybrid
Location: Folsom • Arizona, California, Oregon • 🇺🇸 United States
Visit company websiteSalary
💰 $161,230 - $227,620 per year
Job Level
Senior
About the role
- Are you passionate about computer graphics and disrupting the industry with your innovation and working with leading Engineers on Intel's latest GPU/CPU architecture? Do you love collaborating with diverse teams to help achieve Best-In-Class visual experiences that enable users to immerse themselves in a new visual future? Then AI SOC Engineering team has opportunities for you. Our Hardware development team designs and validates the future of GPU Cores. We are looking for Senior DFT Design Engineer to join our team who are ready to make significant impacts in graphics and visual computing. As a member of the AI SOC Engineering group, you will be responsible for one or more of the following activities: You will work on the design, RTL/GLS validation, automation, and/or timing analysis for Scan/ATPG and/or DFT/JTAG controller You will also contribute or be involved with trace/pattern generation efforts as well as post-silicon enabling, debug support, and/or analysis of the DFx features/content types you are responsible for. Develops the logic design, register transfer level (RTL) coding, and simulation for graphics IPs (including graphics, compute, display, and media) required to generate cell libraries, functional units, and the GPU IP block for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly across verification hierarchies, drives unit level verification, and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Supports SoC customers to ensure high-quality integration of the GPU block. The ideal candidate will exhibit the following traits/skills: Excellent written and verbal communication skills Demonstrate Leadership ability in driving execution Demonstrate teamwork, problem solving and influencing skills Ability to work with different geographical locations
Requirements
- Bachelors Degree in Electrical Engineering, Computer Engineering, or related STEM degree and 5+ years of industry experience OR Masters in Electrical Engineering, Computer Engineering or related STEM degree and 3+ years of industry experience OR PhD in Electrical Engineering, Computer Engineering or related STEM degree and 2+ years of industry experience
- At least one of the key DFT features such as TAP/JTAG, Scan/ATPG or Array DFT (MBIST/PBIST)
- SoC or IP DFT design, integration or verification
- EDA tools such as ATPG tools, Siemens Tessent shell, VCS simulation and/or debug tools.
Benefits
- We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003
ATS Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard skills
DFT designRTL codingGLS validationtiming analysisScan/ATPGJTAG controllertrace generationpattern generationlogic designGPU IP design
Soft skills
communication skillsleadershipteamworkproblem solvinginfluencing skills
