Intel Corporation

IP Enablement Application Engineer

Intel Corporation

full-time

Posted on:

Origin:  • 🇺🇸 United States • Arizona, California, Oregon

Visit company website
AI Apply
Manual Apply

Salary

💰 $153,540 - $216,770 per year

Job Level

Mid-LevelSenior

Tech Stack

PerlPython

About the role

  • Intel Foundry is a systems foundry dedicated to transforming the global semiconductor industry by delivering cutting-edge silicon process and packaging technology leadership for the AI era.
  • The Aerospace, Defense and Government (ADG) - SoC Design and IP Enablement Engineer provides technical support to Intel Foundry Services customers on IP integration issues.
  • Collaborate with internal teams across Intel and external stakeholders such as foundry customers' design teams, IP providers, and EDA vendors on foundational IP integration issue resolution.
  • Create content, application notes and deliver technical training/presentations.
  • Drive quality of design kits, documentation, and assist in tearing down barriers to successful customer design tape-outs.
  • Able to work independently with design team and customers to solve issues either remotely or onsite.
  • Fully own assigned IPs and work with Internal and external customer and help them integrate Intel IPs to SoC and provide technical support.

Requirements

  • US Citizenship required.
  • Ability to obtain and maintain a US Government Security Clearance.
  • Bachelor's degree in Electrical Engineering, Computer Science, or in a STEM related field of study.
  • 3+ years of experience with SOC IP integration.
  • 4+ years of experience in RTL design and DFT using Verilog/System Verilog.
  • 4+ years of experience with VCS, Verdi, Spyglass or equivalent tools.
  • Experience in ASIC or SoC development.
  • Preferred: Active US Government Security Clearance with a minimum of Secret level.
  • Post Graduate degree in Electrical Engineering, Computer Science, or in a STEM related field of study.
  • Experience with one or more industry standard IO interfaces including (ADPLL, GPIO, Digital Thermal Sensors, DDR, LPDDR, PCIE, USB, USB TypeC, Ethernet, etc.)
  • Hands on Experience with customer support in at least one of the following domains: (Memory Design, Memory Compiler Design, eFUSE and or antiFUSE.)
  • Experience with IP integration and design flow challenges within the context of subsystems and SOCs.
  • Experience with IP development.
  • Experience in scripting languages like such as Perl/Tcl/ and Python.