Senior FPGA Engineer
Red 6
Python
ASIC/FPGA Design and Verification Engineer – Lead/Senior/Principal
Boeing
full-time
Posted on:
Origin: • 🇺🇸 United States • California
Visit company websiteSalary
💰 $126,650 - $257,600 per year
Job Level
Senior
Tech Stack
LinuxPerlPythonSubversion
About the role
- Lead FPGA/ASIC designs, including multi-FPGA/ASIC programs and teams, and manage team execution to meet program milestones
- Collaborate with customers, system engineers, and hardware engineers to drive requirements capture and architect digital logic functions to meet mission/customer needs
- Explore trade-space of potential ASIC/FPGA technologies and determine optimal parts weighing Schedule, Cost, Risk, Area, Power (SCRAP) vs. performance
- Implement FPGA/ASIC with latest design practices and tools from block-level micro-architecture, through HDL coding, and physical design realization (through gate-level netlists for ASIC designs)
- Integrate DSP IP from Boeing’s algorithm team and third-party IP as needed
- Perform static timing analysis, LEC, CDC, linting, and other necessary checks to ensure the design is completed on schedule
- Develop Functional Coverage Models and perform Code Coverage to verify designs in simulation
- Create self-checking and reusable test benches from scratch using OOP concepts and leverage UVM to create drivers, monitors, predictors, and scoreboards
- Drive FPGA-based prototyping and validation depending on program and system requirements and complexity
- Validate design through hardware integration test with special test equipment, test-beds, and higher-level systems as needed
- Train and mentor less senior engineers and help build effective project teams
Requirements
- Bachelor of Science degree from an accredited course of study in engineering, engineering technology, chemistry, physics, mathematics, data science, or computer science (Bachelor's Degree or Equivalent)
- 5+ years of ASIC/FPGA design or verification experience (minimum)
- Experience with ASIC/FPGA architectural definition, detailed design implementation and functional verification using SystemVerilog
- Professional experience with hardware-based integration and test of ASIC/FPGA designs
- Proven record of leading ASIC/FPGA design and/or verification teams, including tracking and reporting progress to stakeholders
- Experience performing static timing analysis, LEC, CDC, linting
- Experience developing Functional Coverage Models and closing Code Coverage
- Ability to create self-checking and reusable test benches using Object Oriented Programming concepts and UVM
- Experience with FPGA-based prototyping and hardware integration testing
- Ability to drive requirements capture and architect digital logic functions
- Preferred: 10+ years related work experience or equivalent combination of education and experience
- Preferred: Master’s Degree in EE, Computer Engineering/Science, or related field (or equivalent experience)
- Preferred: Experience with hardware emulators (especially Palladium)
- Proficiency with SystemVerilog Assertions
- Experience with high-speed Serdes interfaces (JESD204C, PCIe, Ethernet)
- Proficient in scripting languages: Make, Perl, Python, etc.
- Experience with revision control systems: svn, cvs, git
- Proficient in Linux environments
- Familiarity with space-based design techniques and radiation mitigation
- Demonstrated history of 1st pass success with ASIC designs
- Export control compliance: must be a "U.S. Person" as defined by 22 C.F.R. §120.15
- Security Clearance: ability to obtain a U.S. Security Clearance (U.S. Citizenship required); interim and/or final U.S. Secret Clearance Post-Start is required
- Visa Sponsorship: Employer will not sponsor applicants for employment visa status
