Lead FPGA Engineer
Red 6
Python
Job Level
SeniorLead
About the role
- Architect and define overall SoC including processing units, hardware accelerators, memory, interconnect, interfaces and analog components.
- Work hand in hand with product architects ensuring hardware architecture meets product goals.
- Define RAS strategies and support architecture of RAS features across Hardware Design and Software implementation.
- Develop hardware architecture models and simulations including RAS metrics (e.g., FIT, AVF).
- Evaluate architectural and micro-architecture options and impacts on PPAC.
- Conduct system-level modelling and analysis to optimize PPAC.
- Collaborate with Software and Firmware teams for system codesign.
- Evaluate new processes, technologies, trends, and industry standards.
- Perform hard and soft IP identification, analysis and selection.
- Lead architecture definition, reviews and provide technical guidance.
- Collaborate with design implementation, verification, physical design, software and firmware teams for development and design convergence.
- Support SoC execution across project milestones and drive dependency resolution.
- Define and develop system-level methodologies, tools, and IPs for efficient scalable SoC development.
Requirements
- Bachelor’s/Master’s/PhD in Electrical Engineering, Computer Engineering or related field
- 10+ years of solid experience in IP/SoC architecture and design for ASIC or FPGA
- Foundational understanding and familiarity with key reliability themes (ECC, CRC, parity, Reed-Solomon, BCH)
- Knowledge of fault isolation, failover, redundancy mechanisms (spare cores, redundant memory channels, retry logic, watchdog timers)
- Familiarity with serviceability features such as logging, telemetry, and predictive failure analysis
- Experience with thermal, voltage, and aging-related failures
- Good knowledge on Design for Testability and Manufacturability and the intersection with RAS
- Experience with architecture trade-offs and design methodologies for PPAC in advanced technologies
- Proficiency in performance modelling, simulation frameworks and scripting
- Strong knowledge in SoC architecture aspects: Clocks, Resets, Power-Sequencing, Power Management, Interrupts, Interconnects, Boot, Virtualization, Security, System Performance, IO technologies, Platform integration
- Experience with RISC-V based Systems
- General knowledge of SoC implementation standards, interconnect (AMBA, AXI, CHI) and interfaces (PCIe, UCIe, I2C, I3C, SPI, JTAG)
- General knowledge of Advanced packaging (2.5D, 3D, SiP, CoWoS) and chiplets
