Engineer

• Own pre- and post-launch performance: plan, execute, and sustain performance validation, debugging, and optimization for adapters, switches, and fabric software—first in lab, then at scale in production
• Lead performance for post-silicon bring-up validation of networking ASICs and end-products (adapters, switches, etc.); driving optimization and characterization against networking metrics and application performance
• Deliver white-glove customer support at scale: reproduce field issues, co-debug in shared/onsite labs, land mitigations and durable fixes, and publish per-customer tuning guides
• Pathfind and optimize forward-looking workloads: drive research and enablement for AI inference (QPS, P99/P99.9, cost/throughput), distributed AI training (NCCL/RCCL collectives), and traditional HPC (manufacturing, life sciences, climate)
• Multi-fabric research & enablement: evaluate and tune Cornelis/Omni-Path, Ethernet/RoCEv2, and InfiniBand across topologies (Clos/fat-tree/dragonfly), routing (ECMP/adaptive), and congestion control (credit, PFC/ECN/DCQCN)
• Explore platform designs & tunings end-to-end: CPU/GPU NUMA placement, PCIe/GPU-Direct, BIOS/firmware, PTP/1588, switch/NIC QoS & scheduling, queue depths, microburst tolerance, ECN mark rates, retransmits, fairness
• Design credible experiments: synthesize representative traffic, replay workload traces, and run on-cluster A/B tests with statistically sound comparisons (P50/P90/P99)

Principal Performance Engineer

Senior Device Lab Engineer

Cyber Splunk Engineer

Senior Forward Deployed Engineer

Quality Process Engineer

Process Engineer – Service Delivery